Module esp32c2_hal::pac::spi2::din_mode

SPI input delay mode configuration

Structs

DIN_MODE_SPEC

SPI input delay mode configuration

R

Register DIN_MODE reader

Type Definitions

DIN0_MODE_R

Field DIN0_MODE reader - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.

DIN1_MODE_R

Field DIN1_MODE reader - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.

DIN2_MODE_R

Field DIN2_MODE reader - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.

DIN3_MODE_R

Field DIN3_MODE reader - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.

DIN4_MODE_R

Field DIN4_MODE reader - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.

DIN5_MODE_R

Field DIN5_MODE reader - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.

DIN6_MODE_R

Field DIN6_MODE reader - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.

DIN7_MODE_R

Field DIN7_MODE reader - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.

TIMING_HCLK_ACTIVE_R

Field TIMING_HCLK_ACTIVE reader - 1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF state.