esp32/sdhost/
clk_edge_sel.rs

1#[doc = "Register `CLK_EDGE_SEL` reader"]
2pub type R = crate::R<CLK_EDGE_SEL_SPEC>;
3#[doc = "Register `CLK_EDGE_SEL` writer"]
4pub type W = crate::W<CLK_EDGE_SEL_SPEC>;
5#[doc = "Field `CCLKIN_EDGE_DRV_SEL` reader - It's used to select the clock phase of the output signal from phase 0, phase 90, phase 180, phase 270."]
6pub type CCLKIN_EDGE_DRV_SEL_R = crate::FieldReader;
7#[doc = "Field `CCLKIN_EDGE_DRV_SEL` writer - It's used to select the clock phase of the output signal from phase 0, phase 90, phase 180, phase 270."]
8pub type CCLKIN_EDGE_DRV_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
9#[doc = "Field `CCLKIN_EDGE_SAM_SEL` reader - It's used to select the clock phase of the input signal from phase 0, phase 90, phase 180, phase 270."]
10pub type CCLKIN_EDGE_SAM_SEL_R = crate::FieldReader;
11#[doc = "Field `CCLKIN_EDGE_SAM_SEL` writer - It's used to select the clock phase of the input signal from phase 0, phase 90, phase 180, phase 270."]
12pub type CCLKIN_EDGE_SAM_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
13#[doc = "Field `CCLKIN_EDGE_SLF_SEL` reader - It's used to select the clock phase of the internal signal from phase 0, phase 90, phase 180, phase 270."]
14pub type CCLKIN_EDGE_SLF_SEL_R = crate::FieldReader;
15#[doc = "Field `CCLKIN_EDGE_SLF_SEL` writer - It's used to select the clock phase of the internal signal from phase 0, phase 90, phase 180, phase 270."]
16pub type CCLKIN_EDGE_SLF_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
17#[doc = "Field `CCLLKIN_EDGE_H` reader - The high level of the divider clock. The value should be smaller than CCLKIN_EDGE_L."]
18pub type CCLLKIN_EDGE_H_R = crate::FieldReader;
19#[doc = "Field `CCLLKIN_EDGE_H` writer - The high level of the divider clock. The value should be smaller than CCLKIN_EDGE_L."]
20pub type CCLLKIN_EDGE_H_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
21#[doc = "Field `CCLLKIN_EDGE_L` reader - The low level of the divider clock. The value should be larger than CCLKIN_EDGE_H."]
22pub type CCLLKIN_EDGE_L_R = crate::FieldReader;
23#[doc = "Field `CCLLKIN_EDGE_L` writer - The low level of the divider clock. The value should be larger than CCLKIN_EDGE_H."]
24pub type CCLLKIN_EDGE_L_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
25#[doc = "Field `CCLLKIN_EDGE_N` reader - The value should be equal to CCLKIN_EDGE_L."]
26pub type CCLLKIN_EDGE_N_R = crate::FieldReader;
27#[doc = "Field `CCLLKIN_EDGE_N` writer - The value should be equal to CCLKIN_EDGE_L."]
28pub type CCLLKIN_EDGE_N_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
29#[doc = "Field `ESDIO_MODE` reader - Enable esdio mode."]
30pub type ESDIO_MODE_R = crate::BitReader;
31#[doc = "Field `ESDIO_MODE` writer - Enable esdio mode."]
32pub type ESDIO_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `ESD_MODE` reader - Enable esd mode."]
34pub type ESD_MODE_R = crate::BitReader;
35#[doc = "Field `ESD_MODE` writer - Enable esd mode."]
36pub type ESD_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `CCLK_EN` reader - Sdio clock enable"]
38pub type CCLK_EN_R = crate::BitReader;
39#[doc = "Field `CCLK_EN` writer - Sdio clock enable"]
40pub type CCLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
41impl R {
42    #[doc = "Bits 0:2 - It's used to select the clock phase of the output signal from phase 0, phase 90, phase 180, phase 270."]
43    #[inline(always)]
44    pub fn cclkin_edge_drv_sel(&self) -> CCLKIN_EDGE_DRV_SEL_R {
45        CCLKIN_EDGE_DRV_SEL_R::new((self.bits & 7) as u8)
46    }
47    #[doc = "Bits 3:5 - It's used to select the clock phase of the input signal from phase 0, phase 90, phase 180, phase 270."]
48    #[inline(always)]
49    pub fn cclkin_edge_sam_sel(&self) -> CCLKIN_EDGE_SAM_SEL_R {
50        CCLKIN_EDGE_SAM_SEL_R::new(((self.bits >> 3) & 7) as u8)
51    }
52    #[doc = "Bits 6:8 - It's used to select the clock phase of the internal signal from phase 0, phase 90, phase 180, phase 270."]
53    #[inline(always)]
54    pub fn cclkin_edge_slf_sel(&self) -> CCLKIN_EDGE_SLF_SEL_R {
55        CCLKIN_EDGE_SLF_SEL_R::new(((self.bits >> 6) & 7) as u8)
56    }
57    #[doc = "Bits 9:12 - The high level of the divider clock. The value should be smaller than CCLKIN_EDGE_L."]
58    #[inline(always)]
59    pub fn ccllkin_edge_h(&self) -> CCLLKIN_EDGE_H_R {
60        CCLLKIN_EDGE_H_R::new(((self.bits >> 9) & 0x0f) as u8)
61    }
62    #[doc = "Bits 13:16 - The low level of the divider clock. The value should be larger than CCLKIN_EDGE_H."]
63    #[inline(always)]
64    pub fn ccllkin_edge_l(&self) -> CCLLKIN_EDGE_L_R {
65        CCLLKIN_EDGE_L_R::new(((self.bits >> 13) & 0x0f) as u8)
66    }
67    #[doc = "Bits 17:20 - The value should be equal to CCLKIN_EDGE_L."]
68    #[inline(always)]
69    pub fn ccllkin_edge_n(&self) -> CCLLKIN_EDGE_N_R {
70        CCLLKIN_EDGE_N_R::new(((self.bits >> 17) & 0x0f) as u8)
71    }
72    #[doc = "Bit 21 - Enable esdio mode."]
73    #[inline(always)]
74    pub fn esdio_mode(&self) -> ESDIO_MODE_R {
75        ESDIO_MODE_R::new(((self.bits >> 21) & 1) != 0)
76    }
77    #[doc = "Bit 22 - Enable esd mode."]
78    #[inline(always)]
79    pub fn esd_mode(&self) -> ESD_MODE_R {
80        ESD_MODE_R::new(((self.bits >> 22) & 1) != 0)
81    }
82    #[doc = "Bit 23 - Sdio clock enable"]
83    #[inline(always)]
84    pub fn cclk_en(&self) -> CCLK_EN_R {
85        CCLK_EN_R::new(((self.bits >> 23) & 1) != 0)
86    }
87}
88#[cfg(feature = "impl-register-debug")]
89impl core::fmt::Debug for R {
90    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
91        f.debug_struct("CLK_EDGE_SEL")
92            .field("cclkin_edge_drv_sel", &self.cclkin_edge_drv_sel())
93            .field("cclkin_edge_sam_sel", &self.cclkin_edge_sam_sel())
94            .field("cclkin_edge_slf_sel", &self.cclkin_edge_slf_sel())
95            .field("ccllkin_edge_h", &self.ccllkin_edge_h())
96            .field("ccllkin_edge_l", &self.ccllkin_edge_l())
97            .field("ccllkin_edge_n", &self.ccllkin_edge_n())
98            .field("esdio_mode", &self.esdio_mode())
99            .field("esd_mode", &self.esd_mode())
100            .field("cclk_en", &self.cclk_en())
101            .finish()
102    }
103}
104impl W {
105    #[doc = "Bits 0:2 - It's used to select the clock phase of the output signal from phase 0, phase 90, phase 180, phase 270."]
106    #[inline(always)]
107    pub fn cclkin_edge_drv_sel(&mut self) -> CCLKIN_EDGE_DRV_SEL_W<CLK_EDGE_SEL_SPEC> {
108        CCLKIN_EDGE_DRV_SEL_W::new(self, 0)
109    }
110    #[doc = "Bits 3:5 - It's used to select the clock phase of the input signal from phase 0, phase 90, phase 180, phase 270."]
111    #[inline(always)]
112    pub fn cclkin_edge_sam_sel(&mut self) -> CCLKIN_EDGE_SAM_SEL_W<CLK_EDGE_SEL_SPEC> {
113        CCLKIN_EDGE_SAM_SEL_W::new(self, 3)
114    }
115    #[doc = "Bits 6:8 - It's used to select the clock phase of the internal signal from phase 0, phase 90, phase 180, phase 270."]
116    #[inline(always)]
117    pub fn cclkin_edge_slf_sel(&mut self) -> CCLKIN_EDGE_SLF_SEL_W<CLK_EDGE_SEL_SPEC> {
118        CCLKIN_EDGE_SLF_SEL_W::new(self, 6)
119    }
120    #[doc = "Bits 9:12 - The high level of the divider clock. The value should be smaller than CCLKIN_EDGE_L."]
121    #[inline(always)]
122    pub fn ccllkin_edge_h(&mut self) -> CCLLKIN_EDGE_H_W<CLK_EDGE_SEL_SPEC> {
123        CCLLKIN_EDGE_H_W::new(self, 9)
124    }
125    #[doc = "Bits 13:16 - The low level of the divider clock. The value should be larger than CCLKIN_EDGE_H."]
126    #[inline(always)]
127    pub fn ccllkin_edge_l(&mut self) -> CCLLKIN_EDGE_L_W<CLK_EDGE_SEL_SPEC> {
128        CCLLKIN_EDGE_L_W::new(self, 13)
129    }
130    #[doc = "Bits 17:20 - The value should be equal to CCLKIN_EDGE_L."]
131    #[inline(always)]
132    pub fn ccllkin_edge_n(&mut self) -> CCLLKIN_EDGE_N_W<CLK_EDGE_SEL_SPEC> {
133        CCLLKIN_EDGE_N_W::new(self, 17)
134    }
135    #[doc = "Bit 21 - Enable esdio mode."]
136    #[inline(always)]
137    pub fn esdio_mode(&mut self) -> ESDIO_MODE_W<CLK_EDGE_SEL_SPEC> {
138        ESDIO_MODE_W::new(self, 21)
139    }
140    #[doc = "Bit 22 - Enable esd mode."]
141    #[inline(always)]
142    pub fn esd_mode(&mut self) -> ESD_MODE_W<CLK_EDGE_SEL_SPEC> {
143        ESD_MODE_W::new(self, 22)
144    }
145    #[doc = "Bit 23 - Sdio clock enable"]
146    #[inline(always)]
147    pub fn cclk_en(&mut self) -> CCLK_EN_W<CLK_EDGE_SEL_SPEC> {
148        CCLK_EN_W::new(self, 23)
149    }
150}
151#[doc = "SDIO control register.\n\nYou can [`read`](crate::Reg::read) this register and get [`clk_edge_sel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_edge_sel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
152pub struct CLK_EDGE_SEL_SPEC;
153impl crate::RegisterSpec for CLK_EDGE_SEL_SPEC {
154    type Ux = u32;
155}
156#[doc = "`read()` method returns [`clk_edge_sel::R`](R) reader structure"]
157impl crate::Readable for CLK_EDGE_SEL_SPEC {}
158#[doc = "`write(|w| ..)` method takes [`clk_edge_sel::W`](W) writer structure"]
159impl crate::Writable for CLK_EDGE_SEL_SPEC {
160    type Safety = crate::Unsafe;
161    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
162    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
163}
164#[doc = "`reset()` method sets CLK_EDGE_SEL to value 0x0082_0200"]
165impl crate::Resettable for CLK_EDGE_SEL_SPEC {
166    const RESET_VALUE: u32 = 0x0082_0200;
167}
esp32/sdhost/clk_edge_sel.rs

esp32/sdhost/
clk_edge_sel.rs
