1#[doc = "Register `INT_CLR` writer"]
2pub type W = crate::W<INT_CLR_SPEC>;
3#[doc = "Field `HSTIMER_OVF(0-3)` writer - Set this bit to clear high speed channel%s counter overflow interrupt."]
4pub type HSTIMER_OVF_W<'a, REG> = crate::BitWriter1C<'a, REG>;
5#[doc = "Field `LSTIMER_OVF(0-3)` writer - Set this bit to clear low speed channel%s counter overflow interrupt."]
6pub type LSTIMER_OVF_W<'a, REG> = crate::BitWriter1C<'a, REG>;
7#[doc = "Field `DUTY_CHNG_END_HSCH(0-7)` writer - Set this bit to clear high speed channel %s duty change done interrupt."]
8pub type DUTY_CHNG_END_HSCH_W<'a, REG> = crate::BitWriter1C<'a, REG>;
9#[doc = "Field `DUTY_CHNG_END_LSCH(0-7)` writer - Set this bit to clear low speed channel %s duty change done interrupt."]
10pub type DUTY_CHNG_END_LSCH_W<'a, REG> = crate::BitWriter1C<'a, REG>;
11#[cfg(feature = "impl-register-debug")]
12impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
13 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
14 write!(f, "(not readable)")
15 }
16}
17impl W {
18 #[doc = "Set this bit to clear high speed channel(0-3) counter overflow interrupt."]
19 #[doc = ""]
20 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `HSTIMER0_OVF` field.</div>"]
21 #[inline(always)]
22 pub fn hstimer_ovf(&mut self, n: u8) -> HSTIMER_OVF_W<INT_CLR_SPEC> {
23 #[allow(clippy::no_effect)]
24 [(); 4][n as usize];
25 HSTIMER_OVF_W::new(self, n)
26 }
27 #[doc = "Bit 0 - Set this bit to clear high speed channel0 counter overflow interrupt."]
28 #[inline(always)]
29 pub fn hstimer0_ovf(&mut self) -> HSTIMER_OVF_W<INT_CLR_SPEC> {
30 HSTIMER_OVF_W::new(self, 0)
31 }
32 #[doc = "Bit 1 - Set this bit to clear high speed channel1 counter overflow interrupt."]
33 #[inline(always)]
34 pub fn hstimer1_ovf(&mut self) -> HSTIMER_OVF_W<INT_CLR_SPEC> {
35 HSTIMER_OVF_W::new(self, 1)
36 }
37 #[doc = "Bit 2 - Set this bit to clear high speed channel2 counter overflow interrupt."]
38 #[inline(always)]
39 pub fn hstimer2_ovf(&mut self) -> HSTIMER_OVF_W<INT_CLR_SPEC> {
40 HSTIMER_OVF_W::new(self, 2)
41 }
42 #[doc = "Bit 3 - Set this bit to clear high speed channel3 counter overflow interrupt."]
43 #[inline(always)]
44 pub fn hstimer3_ovf(&mut self) -> HSTIMER_OVF_W<INT_CLR_SPEC> {
45 HSTIMER_OVF_W::new(self, 3)
46 }
47 #[doc = "Set this bit to clear low speed channel(0-3) counter overflow interrupt."]
48 #[doc = ""]
49 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `LSTIMER0_OVF` field.</div>"]
50 #[inline(always)]
51 pub fn lstimer_ovf(&mut self, n: u8) -> LSTIMER_OVF_W<INT_CLR_SPEC> {
52 #[allow(clippy::no_effect)]
53 [(); 4][n as usize];
54 LSTIMER_OVF_W::new(self, n + 4)
55 }
56 #[doc = "Bit 4 - Set this bit to clear low speed channel0 counter overflow interrupt."]
57 #[inline(always)]
58 pub fn lstimer0_ovf(&mut self) -> LSTIMER_OVF_W<INT_CLR_SPEC> {
59 LSTIMER_OVF_W::new(self, 4)
60 }
61 #[doc = "Bit 5 - Set this bit to clear low speed channel1 counter overflow interrupt."]
62 #[inline(always)]
63 pub fn lstimer1_ovf(&mut self) -> LSTIMER_OVF_W<INT_CLR_SPEC> {
64 LSTIMER_OVF_W::new(self, 5)
65 }
66 #[doc = "Bit 6 - Set this bit to clear low speed channel2 counter overflow interrupt."]
67 #[inline(always)]
68 pub fn lstimer2_ovf(&mut self) -> LSTIMER_OVF_W<INT_CLR_SPEC> {
69 LSTIMER_OVF_W::new(self, 6)
70 }
71 #[doc = "Bit 7 - Set this bit to clear low speed channel3 counter overflow interrupt."]
72 #[inline(always)]
73 pub fn lstimer3_ovf(&mut self) -> LSTIMER_OVF_W<INT_CLR_SPEC> {
74 LSTIMER_OVF_W::new(self, 7)
75 }
76 #[doc = "Set this bit to clear high speed channel (0-7) duty change done interrupt."]
77 #[doc = ""]
78 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `DUTY_CHNG_END_HSCH0` field.</div>"]
79 #[inline(always)]
80 pub fn duty_chng_end_hsch(&mut self, n: u8) -> DUTY_CHNG_END_HSCH_W<INT_CLR_SPEC> {
81 #[allow(clippy::no_effect)]
82 [(); 8][n as usize];
83 DUTY_CHNG_END_HSCH_W::new(self, n + 8)
84 }
85 #[doc = "Bit 8 - Set this bit to clear high speed channel 0 duty change done interrupt."]
86 #[inline(always)]
87 pub fn duty_chng_end_hsch0(&mut self) -> DUTY_CHNG_END_HSCH_W<INT_CLR_SPEC> {
88 DUTY_CHNG_END_HSCH_W::new(self, 8)
89 }
90 #[doc = "Bit 9 - Set this bit to clear high speed channel 1 duty change done interrupt."]
91 #[inline(always)]
92 pub fn duty_chng_end_hsch1(&mut self) -> DUTY_CHNG_END_HSCH_W<INT_CLR_SPEC> {
93 DUTY_CHNG_END_HSCH_W::new(self, 9)
94 }
95 #[doc = "Bit 10 - Set this bit to clear high speed channel 2 duty change done interrupt."]
96 #[inline(always)]
97 pub fn duty_chng_end_hsch2(&mut self) -> DUTY_CHNG_END_HSCH_W<INT_CLR_SPEC> {
98 DUTY_CHNG_END_HSCH_W::new(self, 10)
99 }
100 #[doc = "Bit 11 - Set this bit to clear high speed channel 3 duty change done interrupt."]
101 #[inline(always)]
102 pub fn duty_chng_end_hsch3(&mut self) -> DUTY_CHNG_END_HSCH_W<INT_CLR_SPEC> {
103 DUTY_CHNG_END_HSCH_W::new(self, 11)
104 }
105 #[doc = "Bit 12 - Set this bit to clear high speed channel 4 duty change done interrupt."]
106 #[inline(always)]
107 pub fn duty_chng_end_hsch4(&mut self) -> DUTY_CHNG_END_HSCH_W<INT_CLR_SPEC> {
108 DUTY_CHNG_END_HSCH_W::new(self, 12)
109 }
110 #[doc = "Bit 13 - Set this bit to clear high speed channel 5 duty change done interrupt."]
111 #[inline(always)]
112 pub fn duty_chng_end_hsch5(&mut self) -> DUTY_CHNG_END_HSCH_W<INT_CLR_SPEC> {
113 DUTY_CHNG_END_HSCH_W::new(self, 13)
114 }
115 #[doc = "Bit 14 - Set this bit to clear high speed channel 6 duty change done interrupt."]
116 #[inline(always)]
117 pub fn duty_chng_end_hsch6(&mut self) -> DUTY_CHNG_END_HSCH_W<INT_CLR_SPEC> {
118 DUTY_CHNG_END_HSCH_W::new(self, 14)
119 }
120 #[doc = "Bit 15 - Set this bit to clear high speed channel 7 duty change done interrupt."]
121 #[inline(always)]
122 pub fn duty_chng_end_hsch7(&mut self) -> DUTY_CHNG_END_HSCH_W<INT_CLR_SPEC> {
123 DUTY_CHNG_END_HSCH_W::new(self, 15)
124 }
125 #[doc = "Set this bit to clear low speed channel (0-7) duty change done interrupt."]
126 #[doc = ""]
127 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `DUTY_CHNG_END_LSCH0` field.</div>"]
128 #[inline(always)]
129 pub fn duty_chng_end_lsch(&mut self, n: u8) -> DUTY_CHNG_END_LSCH_W<INT_CLR_SPEC> {
130 #[allow(clippy::no_effect)]
131 [(); 8][n as usize];
132 DUTY_CHNG_END_LSCH_W::new(self, n + 16)
133 }
134 #[doc = "Bit 16 - Set this bit to clear low speed channel 0 duty change done interrupt."]
135 #[inline(always)]
136 pub fn duty_chng_end_lsch0(&mut self) -> DUTY_CHNG_END_LSCH_W<INT_CLR_SPEC> {
137 DUTY_CHNG_END_LSCH_W::new(self, 16)
138 }
139 #[doc = "Bit 17 - Set this bit to clear low speed channel 1 duty change done interrupt."]
140 #[inline(always)]
141 pub fn duty_chng_end_lsch1(&mut self) -> DUTY_CHNG_END_LSCH_W<INT_CLR_SPEC> {
142 DUTY_CHNG_END_LSCH_W::new(self, 17)
143 }
144 #[doc = "Bit 18 - Set this bit to clear low speed channel 2 duty change done interrupt."]
145 #[inline(always)]
146 pub fn duty_chng_end_lsch2(&mut self) -> DUTY_CHNG_END_LSCH_W<INT_CLR_SPEC> {
147 DUTY_CHNG_END_LSCH_W::new(self, 18)
148 }
149 #[doc = "Bit 19 - Set this bit to clear low speed channel 3 duty change done interrupt."]
150 #[inline(always)]
151 pub fn duty_chng_end_lsch3(&mut self) -> DUTY_CHNG_END_LSCH_W<INT_CLR_SPEC> {
152 DUTY_CHNG_END_LSCH_W::new(self, 19)
153 }
154 #[doc = "Bit 20 - Set this bit to clear low speed channel 4 duty change done interrupt."]
155 #[inline(always)]
156 pub fn duty_chng_end_lsch4(&mut self) -> DUTY_CHNG_END_LSCH_W<INT_CLR_SPEC> {
157 DUTY_CHNG_END_LSCH_W::new(self, 20)
158 }
159 #[doc = "Bit 21 - Set this bit to clear low speed channel 5 duty change done interrupt."]
160 #[inline(always)]
161 pub fn duty_chng_end_lsch5(&mut self) -> DUTY_CHNG_END_LSCH_W<INT_CLR_SPEC> {
162 DUTY_CHNG_END_LSCH_W::new(self, 21)
163 }
164 #[doc = "Bit 22 - Set this bit to clear low speed channel 6 duty change done interrupt."]
165 #[inline(always)]
166 pub fn duty_chng_end_lsch6(&mut self) -> DUTY_CHNG_END_LSCH_W<INT_CLR_SPEC> {
167 DUTY_CHNG_END_LSCH_W::new(self, 22)
168 }
169 #[doc = "Bit 23 - Set this bit to clear low speed channel 7 duty change done interrupt."]
170 #[inline(always)]
171 pub fn duty_chng_end_lsch7(&mut self) -> DUTY_CHNG_END_LSCH_W<INT_CLR_SPEC> {
172 DUTY_CHNG_END_LSCH_W::new(self, 23)
173 }
174}
175#[doc = "\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
176pub struct INT_CLR_SPEC;
177impl crate::RegisterSpec for INT_CLR_SPEC {
178 type Ux = u32;
179}
180#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"]
181impl crate::Writable for INT_CLR_SPEC {
182 type Safety = crate::Unsafe;
183 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
184 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x00ff_ffff;
185}
186#[doc = "`reset()` method sets INT_CLR to value 0"]
187impl crate::Resettable for INT_CLR_SPEC {
188 const RESET_VALUE: u32 = 0;
189}