esp32/gpio/
acpu_int.rs

1#[doc = "Register `ACPU_INT` reader"]
2pub type R = crate::R<ACPU_INT_SPEC>;
3#[doc = "Field `APPCPU_INT` reader - GPIO0~31 APP CPU interrupt status"]
4pub type APPCPU_INT_R = crate::FieldReader<u32>;
5impl R {
6    #[doc = "Bits 0:31 - GPIO0~31 APP CPU interrupt status"]
7    #[inline(always)]
8    pub fn appcpu_int(&self) -> APPCPU_INT_R {
9        APPCPU_INT_R::new(self.bits)
10    }
11}
12#[cfg(feature = "impl-register-debug")]
13impl core::fmt::Debug for R {
14    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
15        f.debug_struct("ACPU_INT")
16            .field("appcpu_int", &self.appcpu_int())
17            .finish()
18    }
19}
20#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`acpu_int::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
21pub struct ACPU_INT_SPEC;
22impl crate::RegisterSpec for ACPU_INT_SPEC {
23    type Ux = u32;
24}
25#[doc = "`read()` method returns [`acpu_int::R`](R) reader structure"]
26impl crate::Readable for ACPU_INT_SPEC {}
27#[doc = "`reset()` method sets ACPU_INT to value 0"]
28impl crate::Resettable for ACPU_INT_SPEC {
29    const RESET_VALUE: u32 = 0;
30}
esp32/gpio/acpu_int.rs

esp32/gpio/
acpu_int.rs
