1#[doc = "Register `CONF0` reader"]
2pub type R = crate::R<CONF0_SPEC>;
3#[doc = "Register `CONF0` writer"]
4pub type W = crate::W<CONF0_SPEC>;
5#[doc = "Field `IN_RST` reader - Set this bit to reset in link operations."]
6pub type IN_RST_R = crate::BitReader;
7#[doc = "Field `IN_RST` writer - Set this bit to reset in link operations."]
8pub type IN_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `OUT_RST` reader - Set this bit to reset out link operations."]
10pub type OUT_RST_R = crate::BitReader;
11#[doc = "Field `OUT_RST` writer - Set this bit to reset out link operations."]
12pub type OUT_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `AHBM_FIFO_RST` reader - Set this bit to reset dma ahb fifo."]
14pub type AHBM_FIFO_RST_R = crate::BitReader;
15#[doc = "Field `AHBM_FIFO_RST` writer - Set this bit to reset dma ahb fifo."]
16pub type AHBM_FIFO_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `AHBM_RST` reader - Set this bit to reset dma ahb interface."]
18pub type AHBM_RST_R = crate::BitReader;
19#[doc = "Field `AHBM_RST` writer - Set this bit to reset dma ahb interface."]
20pub type AHBM_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `IN_LOOP_TEST` reader - Set this bit to enable loop test for in links."]
22pub type IN_LOOP_TEST_R = crate::BitReader;
23#[doc = "Field `IN_LOOP_TEST` writer - Set this bit to enable loop test for in links."]
24pub type IN_LOOP_TEST_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `OUT_LOOP_TEST` reader - Set this bit to enable loop test for out links."]
26pub type OUT_LOOP_TEST_R = crate::BitReader;
27#[doc = "Field `OUT_LOOP_TEST` writer - Set this bit to enable loop test for out links."]
28pub type OUT_LOOP_TEST_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `OUT_AUTO_WRBACK` reader - when in link's length is 0 go on to use the next in link automatically."]
30pub type OUT_AUTO_WRBACK_R = crate::BitReader;
31#[doc = "Field `OUT_AUTO_WRBACK` writer - when in link's length is 0 go on to use the next in link automatically."]
32pub type OUT_AUTO_WRBACK_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `OUT_NO_RESTART_CLR` reader - don't use"]
34pub type OUT_NO_RESTART_CLR_R = crate::BitReader;
35#[doc = "Field `OUT_NO_RESTART_CLR` writer - don't use"]
36pub type OUT_NO_RESTART_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `OUT_EOF_MODE` reader - Set this bit to produce eof after DMA pops all data clear this bit to produce eof after DMA pushes all data"]
38pub type OUT_EOF_MODE_R = crate::BitReader;
39#[doc = "Field `OUT_EOF_MODE` writer - Set this bit to produce eof after DMA pops all data clear this bit to produce eof after DMA pushes all data"]
40pub type OUT_EOF_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `UART0_CE` reader - Set this bit to use UART to transmit or receive data."]
42pub type UART0_CE_R = crate::BitReader;
43#[doc = "Field `UART0_CE` writer - Set this bit to use UART to transmit or receive data."]
44pub type UART0_CE_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `UART1_CE` reader - Set this bit to use UART1 to transmit or receive data."]
46pub type UART1_CE_R = crate::BitReader;
47#[doc = "Field `UART1_CE` writer - Set this bit to use UART1 to transmit or receive data."]
48pub type UART1_CE_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `UART2_CE` reader - Set this bit to use UART2 to transmit or receive data."]
50pub type UART2_CE_R = crate::BitReader;
51#[doc = "Field `UART2_CE` writer - Set this bit to use UART2 to transmit or receive data."]
52pub type UART2_CE_W<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `OUTDSCR_BURST_EN` reader - Set this bit to enable DMA in links to use burst mode."]
54pub type OUTDSCR_BURST_EN_R = crate::BitReader;
55#[doc = "Field `OUTDSCR_BURST_EN` writer - Set this bit to enable DMA in links to use burst mode."]
56pub type OUTDSCR_BURST_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
57#[doc = "Field `INDSCR_BURST_EN` reader - Set this bit to enable DMA out links to use burst mode."]
58pub type INDSCR_BURST_EN_R = crate::BitReader;
59#[doc = "Field `INDSCR_BURST_EN` writer - Set this bit to enable DMA out links to use burst mode."]
60pub type INDSCR_BURST_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
61#[doc = "Field `OUT_DATA_BURST_EN` reader - Set this bit to enable DMA burst MODE"]
62pub type OUT_DATA_BURST_EN_R = crate::BitReader;
63#[doc = "Field `OUT_DATA_BURST_EN` writer - Set this bit to enable DMA burst MODE"]
64pub type OUT_DATA_BURST_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
65#[doc = "Field `MEM_TRANS_EN` reader - "]
66pub type MEM_TRANS_EN_R = crate::BitReader;
67#[doc = "Field `MEM_TRANS_EN` writer - "]
68pub type MEM_TRANS_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
69#[doc = "Field `SEPER_EN` reader - Set this bit to use special char to separate the data frame."]
70pub type SEPER_EN_R = crate::BitReader;
71#[doc = "Field `SEPER_EN` writer - Set this bit to use special char to separate the data frame."]
72pub type SEPER_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
73#[doc = "Field `HEAD_EN` reader - Set this bit to enable to use head packet before the data frame."]
74pub type HEAD_EN_R = crate::BitReader;
75#[doc = "Field `HEAD_EN` writer - Set this bit to enable to use head packet before the data frame."]
76pub type HEAD_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
77#[doc = "Field `CRC_REC_EN` reader - Set this bit to enable receiver''s ability of crc calculation when crc_en bit in head packet is 1 then there will be crc bytes after data_frame"]
78pub type CRC_REC_EN_R = crate::BitReader;
79#[doc = "Field `CRC_REC_EN` writer - Set this bit to enable receiver''s ability of crc calculation when crc_en bit in head packet is 1 then there will be crc bytes after data_frame"]
80pub type CRC_REC_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
81#[doc = "Field `UART_IDLE_EOF_EN` reader - Set this bit to enable to use idle time when the idle time after data frame is satisfied this means the end of a data frame."]
82pub type UART_IDLE_EOF_EN_R = crate::BitReader;
83#[doc = "Field `UART_IDLE_EOF_EN` writer - Set this bit to enable to use idle time when the idle time after data frame is satisfied this means the end of a data frame."]
84pub type UART_IDLE_EOF_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
85#[doc = "Field `LEN_EOF_EN` reader - Set this bit to enable to use packet_len in packet head when the received data is equal to packet_len this means the end of a data frame."]
86pub type LEN_EOF_EN_R = crate::BitReader;
87#[doc = "Field `LEN_EOF_EN` writer - Set this bit to enable to use packet_len in packet head when the received data is equal to packet_len this means the end of a data frame."]
88pub type LEN_EOF_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
89#[doc = "Field `ENCODE_CRC_EN` reader - Set this bit to enable crc calculation for data frame when bit6 in the head packet is 1."]
90pub type ENCODE_CRC_EN_R = crate::BitReader;
91#[doc = "Field `ENCODE_CRC_EN` writer - Set this bit to enable crc calculation for data frame when bit6 in the head packet is 1."]
92pub type ENCODE_CRC_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
93#[doc = "Field `CLK_EN` reader - Set this bit to enable clock-gating for read or write registers."]
94pub type CLK_EN_R = crate::BitReader;
95#[doc = "Field `CLK_EN` writer - Set this bit to enable clock-gating for read or write registers."]
96pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
97#[doc = "Field `UART_RX_BRK_EOF_EN` reader - Set this bit to enable to use brk char as the end of a data frame."]
98pub type UART_RX_BRK_EOF_EN_R = crate::BitReader;
99#[doc = "Field `UART_RX_BRK_EOF_EN` writer - Set this bit to enable to use brk char as the end of a data frame."]
100pub type UART_RX_BRK_EOF_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
101impl R {
102 #[doc = "Bit 0 - Set this bit to reset in link operations."]
103 #[inline(always)]
104 pub fn in_rst(&self) -> IN_RST_R {
105 IN_RST_R::new((self.bits & 1) != 0)
106 }
107 #[doc = "Bit 1 - Set this bit to reset out link operations."]
108 #[inline(always)]
109 pub fn out_rst(&self) -> OUT_RST_R {
110 OUT_RST_R::new(((self.bits >> 1) & 1) != 0)
111 }
112 #[doc = "Bit 2 - Set this bit to reset dma ahb fifo."]
113 #[inline(always)]
114 pub fn ahbm_fifo_rst(&self) -> AHBM_FIFO_RST_R {
115 AHBM_FIFO_RST_R::new(((self.bits >> 2) & 1) != 0)
116 }
117 #[doc = "Bit 3 - Set this bit to reset dma ahb interface."]
118 #[inline(always)]
119 pub fn ahbm_rst(&self) -> AHBM_RST_R {
120 AHBM_RST_R::new(((self.bits >> 3) & 1) != 0)
121 }
122 #[doc = "Bit 4 - Set this bit to enable loop test for in links."]
123 #[inline(always)]
124 pub fn in_loop_test(&self) -> IN_LOOP_TEST_R {
125 IN_LOOP_TEST_R::new(((self.bits >> 4) & 1) != 0)
126 }
127 #[doc = "Bit 5 - Set this bit to enable loop test for out links."]
128 #[inline(always)]
129 pub fn out_loop_test(&self) -> OUT_LOOP_TEST_R {
130 OUT_LOOP_TEST_R::new(((self.bits >> 5) & 1) != 0)
131 }
132 #[doc = "Bit 6 - when in link's length is 0 go on to use the next in link automatically."]
133 #[inline(always)]
134 pub fn out_auto_wrback(&self) -> OUT_AUTO_WRBACK_R {
135 OUT_AUTO_WRBACK_R::new(((self.bits >> 6) & 1) != 0)
136 }
137 #[doc = "Bit 7 - don't use"]
138 #[inline(always)]
139 pub fn out_no_restart_clr(&self) -> OUT_NO_RESTART_CLR_R {
140 OUT_NO_RESTART_CLR_R::new(((self.bits >> 7) & 1) != 0)
141 }
142 #[doc = "Bit 8 - Set this bit to produce eof after DMA pops all data clear this bit to produce eof after DMA pushes all data"]
143 #[inline(always)]
144 pub fn out_eof_mode(&self) -> OUT_EOF_MODE_R {
145 OUT_EOF_MODE_R::new(((self.bits >> 8) & 1) != 0)
146 }
147 #[doc = "Bit 9 - Set this bit to use UART to transmit or receive data."]
148 #[inline(always)]
149 pub fn uart0_ce(&self) -> UART0_CE_R {
150 UART0_CE_R::new(((self.bits >> 9) & 1) != 0)
151 }
152 #[doc = "Bit 10 - Set this bit to use UART1 to transmit or receive data."]
153 #[inline(always)]
154 pub fn uart1_ce(&self) -> UART1_CE_R {
155 UART1_CE_R::new(((self.bits >> 10) & 1) != 0)
156 }
157 #[doc = "Bit 11 - Set this bit to use UART2 to transmit or receive data."]
158 #[inline(always)]
159 pub fn uart2_ce(&self) -> UART2_CE_R {
160 UART2_CE_R::new(((self.bits >> 11) & 1) != 0)
161 }
162 #[doc = "Bit 12 - Set this bit to enable DMA in links to use burst mode."]
163 #[inline(always)]
164 pub fn outdscr_burst_en(&self) -> OUTDSCR_BURST_EN_R {
165 OUTDSCR_BURST_EN_R::new(((self.bits >> 12) & 1) != 0)
166 }
167 #[doc = "Bit 13 - Set this bit to enable DMA out links to use burst mode."]
168 #[inline(always)]
169 pub fn indscr_burst_en(&self) -> INDSCR_BURST_EN_R {
170 INDSCR_BURST_EN_R::new(((self.bits >> 13) & 1) != 0)
171 }
172 #[doc = "Bit 14 - Set this bit to enable DMA burst MODE"]
173 #[inline(always)]
174 pub fn out_data_burst_en(&self) -> OUT_DATA_BURST_EN_R {
175 OUT_DATA_BURST_EN_R::new(((self.bits >> 14) & 1) != 0)
176 }
177 #[doc = "Bit 15"]
178 #[inline(always)]
179 pub fn mem_trans_en(&self) -> MEM_TRANS_EN_R {
180 MEM_TRANS_EN_R::new(((self.bits >> 15) & 1) != 0)
181 }
182 #[doc = "Bit 16 - Set this bit to use special char to separate the data frame."]
183 #[inline(always)]
184 pub fn seper_en(&self) -> SEPER_EN_R {
185 SEPER_EN_R::new(((self.bits >> 16) & 1) != 0)
186 }
187 #[doc = "Bit 17 - Set this bit to enable to use head packet before the data frame."]
188 #[inline(always)]
189 pub fn head_en(&self) -> HEAD_EN_R {
190 HEAD_EN_R::new(((self.bits >> 17) & 1) != 0)
191 }
192 #[doc = "Bit 18 - Set this bit to enable receiver''s ability of crc calculation when crc_en bit in head packet is 1 then there will be crc bytes after data_frame"]
193 #[inline(always)]
194 pub fn crc_rec_en(&self) -> CRC_REC_EN_R {
195 CRC_REC_EN_R::new(((self.bits >> 18) & 1) != 0)
196 }
197 #[doc = "Bit 19 - Set this bit to enable to use idle time when the idle time after data frame is satisfied this means the end of a data frame."]
198 #[inline(always)]
199 pub fn uart_idle_eof_en(&self) -> UART_IDLE_EOF_EN_R {
200 UART_IDLE_EOF_EN_R::new(((self.bits >> 19) & 1) != 0)
201 }
202 #[doc = "Bit 20 - Set this bit to enable to use packet_len in packet head when the received data is equal to packet_len this means the end of a data frame."]
203 #[inline(always)]
204 pub fn len_eof_en(&self) -> LEN_EOF_EN_R {
205 LEN_EOF_EN_R::new(((self.bits >> 20) & 1) != 0)
206 }
207 #[doc = "Bit 21 - Set this bit to enable crc calculation for data frame when bit6 in the head packet is 1."]
208 #[inline(always)]
209 pub fn encode_crc_en(&self) -> ENCODE_CRC_EN_R {
210 ENCODE_CRC_EN_R::new(((self.bits >> 21) & 1) != 0)
211 }
212 #[doc = "Bit 22 - Set this bit to enable clock-gating for read or write registers."]
213 #[inline(always)]
214 pub fn clk_en(&self) -> CLK_EN_R {
215 CLK_EN_R::new(((self.bits >> 22) & 1) != 0)
216 }
217 #[doc = "Bit 23 - Set this bit to enable to use brk char as the end of a data frame."]
218 #[inline(always)]
219 pub fn uart_rx_brk_eof_en(&self) -> UART_RX_BRK_EOF_EN_R {
220 UART_RX_BRK_EOF_EN_R::new(((self.bits >> 23) & 1) != 0)
221 }
222}
223#[cfg(feature = "impl-register-debug")]
224impl core::fmt::Debug for R {
225 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
226 f.debug_struct("CONF0")
227 .field("in_rst", &self.in_rst())
228 .field("out_rst", &self.out_rst())
229 .field("ahbm_fifo_rst", &self.ahbm_fifo_rst())
230 .field("ahbm_rst", &self.ahbm_rst())
231 .field("in_loop_test", &self.in_loop_test())
232 .field("out_loop_test", &self.out_loop_test())
233 .field("out_auto_wrback", &self.out_auto_wrback())
234 .field("out_no_restart_clr", &self.out_no_restart_clr())
235 .field("out_eof_mode", &self.out_eof_mode())
236 .field("uart0_ce", &self.uart0_ce())
237 .field("uart1_ce", &self.uart1_ce())
238 .field("uart2_ce", &self.uart2_ce())
239 .field("outdscr_burst_en", &self.outdscr_burst_en())
240 .field("indscr_burst_en", &self.indscr_burst_en())
241 .field("out_data_burst_en", &self.out_data_burst_en())
242 .field("mem_trans_en", &self.mem_trans_en())
243 .field("seper_en", &self.seper_en())
244 .field("head_en", &self.head_en())
245 .field("crc_rec_en", &self.crc_rec_en())
246 .field("uart_idle_eof_en", &self.uart_idle_eof_en())
247 .field("len_eof_en", &self.len_eof_en())
248 .field("encode_crc_en", &self.encode_crc_en())
249 .field("clk_en", &self.clk_en())
250 .field("uart_rx_brk_eof_en", &self.uart_rx_brk_eof_en())
251 .finish()
252 }
253}
254impl W {
255 #[doc = "Bit 0 - Set this bit to reset in link operations."]
256 #[inline(always)]
257 pub fn in_rst(&mut self) -> IN_RST_W<CONF0_SPEC> {
258 IN_RST_W::new(self, 0)
259 }
260 #[doc = "Bit 1 - Set this bit to reset out link operations."]
261 #[inline(always)]
262 pub fn out_rst(&mut self) -> OUT_RST_W<CONF0_SPEC> {
263 OUT_RST_W::new(self, 1)
264 }
265 #[doc = "Bit 2 - Set this bit to reset dma ahb fifo."]
266 #[inline(always)]
267 pub fn ahbm_fifo_rst(&mut self) -> AHBM_FIFO_RST_W<CONF0_SPEC> {
268 AHBM_FIFO_RST_W::new(self, 2)
269 }
270 #[doc = "Bit 3 - Set this bit to reset dma ahb interface."]
271 #[inline(always)]
272 pub fn ahbm_rst(&mut self) -> AHBM_RST_W<CONF0_SPEC> {
273 AHBM_RST_W::new(self, 3)
274 }
275 #[doc = "Bit 4 - Set this bit to enable loop test for in links."]
276 #[inline(always)]
277 pub fn in_loop_test(&mut self) -> IN_LOOP_TEST_W<CONF0_SPEC> {
278 IN_LOOP_TEST_W::new(self, 4)
279 }
280 #[doc = "Bit 5 - Set this bit to enable loop test for out links."]
281 #[inline(always)]
282 pub fn out_loop_test(&mut self) -> OUT_LOOP_TEST_W<CONF0_SPEC> {
283 OUT_LOOP_TEST_W::new(self, 5)
284 }
285 #[doc = "Bit 6 - when in link's length is 0 go on to use the next in link automatically."]
286 #[inline(always)]
287 pub fn out_auto_wrback(&mut self) -> OUT_AUTO_WRBACK_W<CONF0_SPEC> {
288 OUT_AUTO_WRBACK_W::new(self, 6)
289 }
290 #[doc = "Bit 7 - don't use"]
291 #[inline(always)]
292 pub fn out_no_restart_clr(&mut self) -> OUT_NO_RESTART_CLR_W<CONF0_SPEC> {
293 OUT_NO_RESTART_CLR_W::new(self, 7)
294 }
295 #[doc = "Bit 8 - Set this bit to produce eof after DMA pops all data clear this bit to produce eof after DMA pushes all data"]
296 #[inline(always)]
297 pub fn out_eof_mode(&mut self) -> OUT_EOF_MODE_W<CONF0_SPEC> {
298 OUT_EOF_MODE_W::new(self, 8)
299 }
300 #[doc = "Bit 9 - Set this bit to use UART to transmit or receive data."]
301 #[inline(always)]
302 pub fn uart0_ce(&mut self) -> UART0_CE_W<CONF0_SPEC> {
303 UART0_CE_W::new(self, 9)
304 }
305 #[doc = "Bit 10 - Set this bit to use UART1 to transmit or receive data."]
306 #[inline(always)]
307 pub fn uart1_ce(&mut self) -> UART1_CE_W<CONF0_SPEC> {
308 UART1_CE_W::new(self, 10)
309 }
310 #[doc = "Bit 11 - Set this bit to use UART2 to transmit or receive data."]
311 #[inline(always)]
312 pub fn uart2_ce(&mut self) -> UART2_CE_W<CONF0_SPEC> {
313 UART2_CE_W::new(self, 11)
314 }
315 #[doc = "Bit 12 - Set this bit to enable DMA in links to use burst mode."]
316 #[inline(always)]
317 pub fn outdscr_burst_en(&mut self) -> OUTDSCR_BURST_EN_W<CONF0_SPEC> {
318 OUTDSCR_BURST_EN_W::new(self, 12)
319 }
320 #[doc = "Bit 13 - Set this bit to enable DMA out links to use burst mode."]
321 #[inline(always)]
322 pub fn indscr_burst_en(&mut self) -> INDSCR_BURST_EN_W<CONF0_SPEC> {
323 INDSCR_BURST_EN_W::new(self, 13)
324 }
325 #[doc = "Bit 14 - Set this bit to enable DMA burst MODE"]
326 #[inline(always)]
327 pub fn out_data_burst_en(&mut self) -> OUT_DATA_BURST_EN_W<CONF0_SPEC> {
328 OUT_DATA_BURST_EN_W::new(self, 14)
329 }
330 #[doc = "Bit 15"]
331 #[inline(always)]
332 pub fn mem_trans_en(&mut self) -> MEM_TRANS_EN_W<CONF0_SPEC> {
333 MEM_TRANS_EN_W::new(self, 15)
334 }
335 #[doc = "Bit 16 - Set this bit to use special char to separate the data frame."]
336 #[inline(always)]
337 pub fn seper_en(&mut self) -> SEPER_EN_W<CONF0_SPEC> {
338 SEPER_EN_W::new(self, 16)
339 }
340 #[doc = "Bit 17 - Set this bit to enable to use head packet before the data frame."]
341 #[inline(always)]
342 pub fn head_en(&mut self) -> HEAD_EN_W<CONF0_SPEC> {
343 HEAD_EN_W::new(self, 17)
344 }
345 #[doc = "Bit 18 - Set this bit to enable receiver''s ability of crc calculation when crc_en bit in head packet is 1 then there will be crc bytes after data_frame"]
346 #[inline(always)]
347 pub fn crc_rec_en(&mut self) -> CRC_REC_EN_W<CONF0_SPEC> {
348 CRC_REC_EN_W::new(self, 18)
349 }
350 #[doc = "Bit 19 - Set this bit to enable to use idle time when the idle time after data frame is satisfied this means the end of a data frame."]
351 #[inline(always)]
352 pub fn uart_idle_eof_en(&mut self) -> UART_IDLE_EOF_EN_W<CONF0_SPEC> {
353 UART_IDLE_EOF_EN_W::new(self, 19)
354 }
355 #[doc = "Bit 20 - Set this bit to enable to use packet_len in packet head when the received data is equal to packet_len this means the end of a data frame."]
356 #[inline(always)]
357 pub fn len_eof_en(&mut self) -> LEN_EOF_EN_W<CONF0_SPEC> {
358 LEN_EOF_EN_W::new(self, 20)
359 }
360 #[doc = "Bit 21 - Set this bit to enable crc calculation for data frame when bit6 in the head packet is 1."]
361 #[inline(always)]
362 pub fn encode_crc_en(&mut self) -> ENCODE_CRC_EN_W<CONF0_SPEC> {
363 ENCODE_CRC_EN_W::new(self, 21)
364 }
365 #[doc = "Bit 22 - Set this bit to enable clock-gating for read or write registers."]
366 #[inline(always)]
367 pub fn clk_en(&mut self) -> CLK_EN_W<CONF0_SPEC> {
368 CLK_EN_W::new(self, 22)
369 }
370 #[doc = "Bit 23 - Set this bit to enable to use brk char as the end of a data frame."]
371 #[inline(always)]
372 pub fn uart_rx_brk_eof_en(&mut self) -> UART_RX_BRK_EOF_EN_W<CONF0_SPEC> {
373 UART_RX_BRK_EOF_EN_W::new(self, 23)
374 }
375}
376#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`conf0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`conf0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
377pub struct CONF0_SPEC;
378impl crate::RegisterSpec for CONF0_SPEC {
379 type Ux = u32;
380}
381#[doc = "`read()` method returns [`conf0::R`](R) reader structure"]
382impl crate::Readable for CONF0_SPEC {}
383#[doc = "`write(|w| ..)` method takes [`conf0::W`](W) writer structure"]
384impl crate::Writable for CONF0_SPEC {
385 type Safety = crate::Unsafe;
386 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
387 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
388}
389#[doc = "`reset()` method sets CONF0 to value 0x0037_0100"]
390impl crate::Resettable for CONF0_SPEC {
391 const RESET_VALUE: u32 = 0x0037_0100;
392}