1#[doc = "Register `CTRL2` reader"]
2pub type R = crate::R<CTRL2_SPEC>;
3#[doc = "Register `CTRL2` writer"]
4pub type W = crate::W<CTRL2_SPEC>;
5#[doc = "Field `SETUP_TIME` reader - (cycles-1) of ¡°prepare¡± phase by spi clock, this bits combined with spi_cs_setup bit."]
6pub type SETUP_TIME_R = crate::FieldReader;
7#[doc = "Field `SETUP_TIME` writer - (cycles-1) of ¡°prepare¡± phase by spi clock, this bits combined with spi_cs_setup bit."]
8pub type SETUP_TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
9#[doc = "Field `HOLD_TIME` reader - delay cycles of cs pin by spi clock, this bits combined with spi_cs_hold bit."]
10pub type HOLD_TIME_R = crate::FieldReader;
11#[doc = "Field `HOLD_TIME` writer - delay cycles of cs pin by spi clock, this bits combined with spi_cs_hold bit."]
12pub type HOLD_TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
13#[doc = "Field `CK_OUT_LOW_MODE` reader - modify spi clock duty ratio when the value is lager than 8, the bits are combined with spi_clkcnt_N bits and spi_clkcnt_L bits."]
14pub type CK_OUT_LOW_MODE_R = crate::FieldReader;
15#[doc = "Field `CK_OUT_LOW_MODE` writer - modify spi clock duty ratio when the value is lager than 8, the bits are combined with spi_clkcnt_N bits and spi_clkcnt_L bits."]
16pub type CK_OUT_LOW_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
17#[doc = "Field `CK_OUT_HIGH_MODE` reader - modify spi clock duty ratio when the value is lager than 8, the bits are combined with spi_clkcnt_N bits and spi_clkcnt_H bits."]
18pub type CK_OUT_HIGH_MODE_R = crate::FieldReader;
19#[doc = "Field `CK_OUT_HIGH_MODE` writer - modify spi clock duty ratio when the value is lager than 8, the bits are combined with spi_clkcnt_N bits and spi_clkcnt_H bits."]
20pub type CK_OUT_HIGH_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
21#[doc = "Field `MISO_DELAY_MODE` reader - MISO signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle"]
22pub type MISO_DELAY_MODE_R = crate::FieldReader;
23#[doc = "Field `MISO_DELAY_MODE` writer - MISO signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle"]
24pub type MISO_DELAY_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
25#[doc = "Field `MISO_DELAY_NUM` reader - MISO signals are delayed by system clock cycles"]
26pub type MISO_DELAY_NUM_R = crate::FieldReader;
27#[doc = "Field `MISO_DELAY_NUM` writer - MISO signals are delayed by system clock cycles"]
28pub type MISO_DELAY_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
29#[doc = "Field `MOSI_DELAY_MODE` reader - MOSI signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle"]
30pub type MOSI_DELAY_MODE_R = crate::FieldReader;
31#[doc = "Field `MOSI_DELAY_MODE` writer - MOSI signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle"]
32pub type MOSI_DELAY_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
33#[doc = "Field `MOSI_DELAY_NUM` reader - MOSI signals are delayed by system clock cycles"]
34pub type MOSI_DELAY_NUM_R = crate::FieldReader;
35#[doc = "Field `MOSI_DELAY_NUM` writer - MOSI signals are delayed by system clock cycles"]
36pub type MOSI_DELAY_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
37#[doc = "Field `CS_DELAY_MODE` reader - spi_cs signal is delayed by spi_clk . 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle"]
38pub type CS_DELAY_MODE_R = crate::FieldReader;
39#[doc = "Field `CS_DELAY_MODE` writer - spi_cs signal is delayed by spi_clk . 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle"]
40pub type CS_DELAY_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
41#[doc = "Field `CS_DELAY_NUM` reader - spi_cs signal is delayed by system clock cycles"]
42pub type CS_DELAY_NUM_R = crate::FieldReader;
43#[doc = "Field `CS_DELAY_NUM` writer - spi_cs signal is delayed by system clock cycles"]
44pub type CS_DELAY_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
45impl R {
46 #[doc = "Bits 0:3 - (cycles-1) of ¡°prepare¡± phase by spi clock, this bits combined with spi_cs_setup bit."]
47 #[inline(always)]
48 pub fn setup_time(&self) -> SETUP_TIME_R {
49 SETUP_TIME_R::new((self.bits & 0x0f) as u8)
50 }
51 #[doc = "Bits 4:7 - delay cycles of cs pin by spi clock, this bits combined with spi_cs_hold bit."]
52 #[inline(always)]
53 pub fn hold_time(&self) -> HOLD_TIME_R {
54 HOLD_TIME_R::new(((self.bits >> 4) & 0x0f) as u8)
55 }
56 #[doc = "Bits 8:11 - modify spi clock duty ratio when the value is lager than 8, the bits are combined with spi_clkcnt_N bits and spi_clkcnt_L bits."]
57 #[inline(always)]
58 pub fn ck_out_low_mode(&self) -> CK_OUT_LOW_MODE_R {
59 CK_OUT_LOW_MODE_R::new(((self.bits >> 8) & 0x0f) as u8)
60 }
61 #[doc = "Bits 12:15 - modify spi clock duty ratio when the value is lager than 8, the bits are combined with spi_clkcnt_N bits and spi_clkcnt_H bits."]
62 #[inline(always)]
63 pub fn ck_out_high_mode(&self) -> CK_OUT_HIGH_MODE_R {
64 CK_OUT_HIGH_MODE_R::new(((self.bits >> 12) & 0x0f) as u8)
65 }
66 #[doc = "Bits 16:17 - MISO signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle"]
67 #[inline(always)]
68 pub fn miso_delay_mode(&self) -> MISO_DELAY_MODE_R {
69 MISO_DELAY_MODE_R::new(((self.bits >> 16) & 3) as u8)
70 }
71 #[doc = "Bits 18:20 - MISO signals are delayed by system clock cycles"]
72 #[inline(always)]
73 pub fn miso_delay_num(&self) -> MISO_DELAY_NUM_R {
74 MISO_DELAY_NUM_R::new(((self.bits >> 18) & 7) as u8)
75 }
76 #[doc = "Bits 21:22 - MOSI signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle"]
77 #[inline(always)]
78 pub fn mosi_delay_mode(&self) -> MOSI_DELAY_MODE_R {
79 MOSI_DELAY_MODE_R::new(((self.bits >> 21) & 3) as u8)
80 }
81 #[doc = "Bits 23:25 - MOSI signals are delayed by system clock cycles"]
82 #[inline(always)]
83 pub fn mosi_delay_num(&self) -> MOSI_DELAY_NUM_R {
84 MOSI_DELAY_NUM_R::new(((self.bits >> 23) & 7) as u8)
85 }
86 #[doc = "Bits 26:27 - spi_cs signal is delayed by spi_clk . 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle"]
87 #[inline(always)]
88 pub fn cs_delay_mode(&self) -> CS_DELAY_MODE_R {
89 CS_DELAY_MODE_R::new(((self.bits >> 26) & 3) as u8)
90 }
91 #[doc = "Bits 28:31 - spi_cs signal is delayed by system clock cycles"]
92 #[inline(always)]
93 pub fn cs_delay_num(&self) -> CS_DELAY_NUM_R {
94 CS_DELAY_NUM_R::new(((self.bits >> 28) & 0x0f) as u8)
95 }
96}
97#[cfg(feature = "impl-register-debug")]
98impl core::fmt::Debug for R {
99 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
100 f.debug_struct("CTRL2")
101 .field("setup_time", &self.setup_time())
102 .field("hold_time", &self.hold_time())
103 .field("ck_out_low_mode", &self.ck_out_low_mode())
104 .field("ck_out_high_mode", &self.ck_out_high_mode())
105 .field("miso_delay_mode", &self.miso_delay_mode())
106 .field("miso_delay_num", &self.miso_delay_num())
107 .field("mosi_delay_mode", &self.mosi_delay_mode())
108 .field("mosi_delay_num", &self.mosi_delay_num())
109 .field("cs_delay_mode", &self.cs_delay_mode())
110 .field("cs_delay_num", &self.cs_delay_num())
111 .finish()
112 }
113}
114impl W {
115 #[doc = "Bits 0:3 - (cycles-1) of ¡°prepare¡± phase by spi clock, this bits combined with spi_cs_setup bit."]
116 #[inline(always)]
117 pub fn setup_time(&mut self) -> SETUP_TIME_W<CTRL2_SPEC> {
118 SETUP_TIME_W::new(self, 0)
119 }
120 #[doc = "Bits 4:7 - delay cycles of cs pin by spi clock, this bits combined with spi_cs_hold bit."]
121 #[inline(always)]
122 pub fn hold_time(&mut self) -> HOLD_TIME_W<CTRL2_SPEC> {
123 HOLD_TIME_W::new(self, 4)
124 }
125 #[doc = "Bits 8:11 - modify spi clock duty ratio when the value is lager than 8, the bits are combined with spi_clkcnt_N bits and spi_clkcnt_L bits."]
126 #[inline(always)]
127 pub fn ck_out_low_mode(&mut self) -> CK_OUT_LOW_MODE_W<CTRL2_SPEC> {
128 CK_OUT_LOW_MODE_W::new(self, 8)
129 }
130 #[doc = "Bits 12:15 - modify spi clock duty ratio when the value is lager than 8, the bits are combined with spi_clkcnt_N bits and spi_clkcnt_H bits."]
131 #[inline(always)]
132 pub fn ck_out_high_mode(&mut self) -> CK_OUT_HIGH_MODE_W<CTRL2_SPEC> {
133 CK_OUT_HIGH_MODE_W::new(self, 12)
134 }
135 #[doc = "Bits 16:17 - MISO signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle"]
136 #[inline(always)]
137 pub fn miso_delay_mode(&mut self) -> MISO_DELAY_MODE_W<CTRL2_SPEC> {
138 MISO_DELAY_MODE_W::new(self, 16)
139 }
140 #[doc = "Bits 18:20 - MISO signals are delayed by system clock cycles"]
141 #[inline(always)]
142 pub fn miso_delay_num(&mut self) -> MISO_DELAY_NUM_W<CTRL2_SPEC> {
143 MISO_DELAY_NUM_W::new(self, 18)
144 }
145 #[doc = "Bits 21:22 - MOSI signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle"]
146 #[inline(always)]
147 pub fn mosi_delay_mode(&mut self) -> MOSI_DELAY_MODE_W<CTRL2_SPEC> {
148 MOSI_DELAY_MODE_W::new(self, 21)
149 }
150 #[doc = "Bits 23:25 - MOSI signals are delayed by system clock cycles"]
151 #[inline(always)]
152 pub fn mosi_delay_num(&mut self) -> MOSI_DELAY_NUM_W<CTRL2_SPEC> {
153 MOSI_DELAY_NUM_W::new(self, 23)
154 }
155 #[doc = "Bits 26:27 - spi_cs signal is delayed by spi_clk . 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle"]
156 #[inline(always)]
157 pub fn cs_delay_mode(&mut self) -> CS_DELAY_MODE_W<CTRL2_SPEC> {
158 CS_DELAY_MODE_W::new(self, 26)
159 }
160 #[doc = "Bits 28:31 - spi_cs signal is delayed by system clock cycles"]
161 #[inline(always)]
162 pub fn cs_delay_num(&mut self) -> CS_DELAY_NUM_W<CTRL2_SPEC> {
163 CS_DELAY_NUM_W::new(self, 28)
164 }
165}
166#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
167pub struct CTRL2_SPEC;
168impl crate::RegisterSpec for CTRL2_SPEC {
169 type Ux = u32;
170}
171#[doc = "`read()` method returns [`ctrl2::R`](R) reader structure"]
172impl crate::Readable for CTRL2_SPEC {}
173#[doc = "`write(|w| ..)` method takes [`ctrl2::W`](W) writer structure"]
174impl crate::Writable for CTRL2_SPEC {
175 type Safety = crate::Unsafe;
176 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
177 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
178}
179#[doc = "`reset()` method sets CTRL2 to value 0x11"]
180impl crate::Resettable for CTRL2_SPEC {
181 const RESET_VALUE: u32 = 0x11;
182}