1#[doc = "Register `CONF1` reader"]
2pub type R = crate::R<CONF1_SPEC>;
3#[doc = "Register `CONF1` writer"]
4pub type W = crate::W<CONF1_SPEC>;
5#[doc = "Field `SLC0_CHECK_OWNER` reader - "]
6pub type SLC0_CHECK_OWNER_R = crate::BitReader;
7#[doc = "Field `SLC0_CHECK_OWNER` writer - "]
8pub type SLC0_CHECK_OWNER_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `SLC0_TX_CHECK_SUM_EN` reader - "]
10pub type SLC0_TX_CHECK_SUM_EN_R = crate::BitReader;
11#[doc = "Field `SLC0_TX_CHECK_SUM_EN` writer - "]
12pub type SLC0_TX_CHECK_SUM_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `SLC0_RX_CHECK_SUM_EN` reader - "]
14pub type SLC0_RX_CHECK_SUM_EN_R = crate::BitReader;
15#[doc = "Field `SLC0_RX_CHECK_SUM_EN` writer - "]
16pub type SLC0_RX_CHECK_SUM_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `CMD_HOLD_EN` reader - "]
18pub type CMD_HOLD_EN_R = crate::BitReader;
19#[doc = "Field `CMD_HOLD_EN` writer - "]
20pub type CMD_HOLD_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `SLC0_LEN_AUTO_CLR` reader - "]
22pub type SLC0_LEN_AUTO_CLR_R = crate::BitReader;
23#[doc = "Field `SLC0_LEN_AUTO_CLR` writer - "]
24pub type SLC0_LEN_AUTO_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `SLC0_TX_STITCH_EN` reader - "]
26pub type SLC0_TX_STITCH_EN_R = crate::BitReader;
27#[doc = "Field `SLC0_TX_STITCH_EN` writer - "]
28pub type SLC0_TX_STITCH_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `SLC0_RX_STITCH_EN` reader - "]
30pub type SLC0_RX_STITCH_EN_R = crate::BitReader;
31#[doc = "Field `SLC0_RX_STITCH_EN` writer - "]
32pub type SLC0_RX_STITCH_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `SLC1_CHECK_OWNER` reader - "]
34pub type SLC1_CHECK_OWNER_R = crate::BitReader;
35#[doc = "Field `SLC1_CHECK_OWNER` writer - "]
36pub type SLC1_CHECK_OWNER_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `SLC1_TX_CHECK_SUM_EN` reader - "]
38pub type SLC1_TX_CHECK_SUM_EN_R = crate::BitReader;
39#[doc = "Field `SLC1_TX_CHECK_SUM_EN` writer - "]
40pub type SLC1_TX_CHECK_SUM_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `SLC1_RX_CHECK_SUM_EN` reader - "]
42pub type SLC1_RX_CHECK_SUM_EN_R = crate::BitReader;
43#[doc = "Field `SLC1_RX_CHECK_SUM_EN` writer - "]
44pub type SLC1_RX_CHECK_SUM_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `HOST_INT_LEVEL_SEL` reader - "]
46pub type HOST_INT_LEVEL_SEL_R = crate::BitReader;
47#[doc = "Field `HOST_INT_LEVEL_SEL` writer - "]
48pub type HOST_INT_LEVEL_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `SLC1_TX_STITCH_EN` reader - "]
50pub type SLC1_TX_STITCH_EN_R = crate::BitReader;
51#[doc = "Field `SLC1_TX_STITCH_EN` writer - "]
52pub type SLC1_TX_STITCH_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `SLC1_RX_STITCH_EN` reader - "]
54pub type SLC1_RX_STITCH_EN_R = crate::BitReader;
55#[doc = "Field `SLC1_RX_STITCH_EN` writer - "]
56pub type SLC1_RX_STITCH_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
57#[doc = "Field `CLK_EN` reader - "]
58pub type CLK_EN_R = crate::BitReader;
59#[doc = "Field `CLK_EN` writer - "]
60pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
61impl R {
62 #[doc = "Bit 0"]
63 #[inline(always)]
64 pub fn slc0_check_owner(&self) -> SLC0_CHECK_OWNER_R {
65 SLC0_CHECK_OWNER_R::new((self.bits & 1) != 0)
66 }
67 #[doc = "Bit 1"]
68 #[inline(always)]
69 pub fn slc0_tx_check_sum_en(&self) -> SLC0_TX_CHECK_SUM_EN_R {
70 SLC0_TX_CHECK_SUM_EN_R::new(((self.bits >> 1) & 1) != 0)
71 }
72 #[doc = "Bit 2"]
73 #[inline(always)]
74 pub fn slc0_rx_check_sum_en(&self) -> SLC0_RX_CHECK_SUM_EN_R {
75 SLC0_RX_CHECK_SUM_EN_R::new(((self.bits >> 2) & 1) != 0)
76 }
77 #[doc = "Bit 3"]
78 #[inline(always)]
79 pub fn cmd_hold_en(&self) -> CMD_HOLD_EN_R {
80 CMD_HOLD_EN_R::new(((self.bits >> 3) & 1) != 0)
81 }
82 #[doc = "Bit 4"]
83 #[inline(always)]
84 pub fn slc0_len_auto_clr(&self) -> SLC0_LEN_AUTO_CLR_R {
85 SLC0_LEN_AUTO_CLR_R::new(((self.bits >> 4) & 1) != 0)
86 }
87 #[doc = "Bit 5"]
88 #[inline(always)]
89 pub fn slc0_tx_stitch_en(&self) -> SLC0_TX_STITCH_EN_R {
90 SLC0_TX_STITCH_EN_R::new(((self.bits >> 5) & 1) != 0)
91 }
92 #[doc = "Bit 6"]
93 #[inline(always)]
94 pub fn slc0_rx_stitch_en(&self) -> SLC0_RX_STITCH_EN_R {
95 SLC0_RX_STITCH_EN_R::new(((self.bits >> 6) & 1) != 0)
96 }
97 #[doc = "Bit 16"]
98 #[inline(always)]
99 pub fn slc1_check_owner(&self) -> SLC1_CHECK_OWNER_R {
100 SLC1_CHECK_OWNER_R::new(((self.bits >> 16) & 1) != 0)
101 }
102 #[doc = "Bit 17"]
103 #[inline(always)]
104 pub fn slc1_tx_check_sum_en(&self) -> SLC1_TX_CHECK_SUM_EN_R {
105 SLC1_TX_CHECK_SUM_EN_R::new(((self.bits >> 17) & 1) != 0)
106 }
107 #[doc = "Bit 18"]
108 #[inline(always)]
109 pub fn slc1_rx_check_sum_en(&self) -> SLC1_RX_CHECK_SUM_EN_R {
110 SLC1_RX_CHECK_SUM_EN_R::new(((self.bits >> 18) & 1) != 0)
111 }
112 #[doc = "Bit 19"]
113 #[inline(always)]
114 pub fn host_int_level_sel(&self) -> HOST_INT_LEVEL_SEL_R {
115 HOST_INT_LEVEL_SEL_R::new(((self.bits >> 19) & 1) != 0)
116 }
117 #[doc = "Bit 20"]
118 #[inline(always)]
119 pub fn slc1_tx_stitch_en(&self) -> SLC1_TX_STITCH_EN_R {
120 SLC1_TX_STITCH_EN_R::new(((self.bits >> 20) & 1) != 0)
121 }
122 #[doc = "Bit 21"]
123 #[inline(always)]
124 pub fn slc1_rx_stitch_en(&self) -> SLC1_RX_STITCH_EN_R {
125 SLC1_RX_STITCH_EN_R::new(((self.bits >> 21) & 1) != 0)
126 }
127 #[doc = "Bit 22"]
128 #[inline(always)]
129 pub fn clk_en(&self) -> CLK_EN_R {
130 CLK_EN_R::new(((self.bits >> 22) & 1) != 0)
131 }
132}
133#[cfg(feature = "impl-register-debug")]
134impl core::fmt::Debug for R {
135 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
136 f.debug_struct("CONF1")
137 .field("slc0_check_owner", &self.slc0_check_owner())
138 .field("slc0_tx_check_sum_en", &self.slc0_tx_check_sum_en())
139 .field("slc0_rx_check_sum_en", &self.slc0_rx_check_sum_en())
140 .field("cmd_hold_en", &self.cmd_hold_en())
141 .field("slc0_len_auto_clr", &self.slc0_len_auto_clr())
142 .field("slc0_tx_stitch_en", &self.slc0_tx_stitch_en())
143 .field("slc0_rx_stitch_en", &self.slc0_rx_stitch_en())
144 .field("slc1_check_owner", &self.slc1_check_owner())
145 .field("slc1_tx_check_sum_en", &self.slc1_tx_check_sum_en())
146 .field("slc1_rx_check_sum_en", &self.slc1_rx_check_sum_en())
147 .field("host_int_level_sel", &self.host_int_level_sel())
148 .field("slc1_tx_stitch_en", &self.slc1_tx_stitch_en())
149 .field("slc1_rx_stitch_en", &self.slc1_rx_stitch_en())
150 .field("clk_en", &self.clk_en())
151 .finish()
152 }
153}
154impl W {
155 #[doc = "Bit 0"]
156 #[inline(always)]
157 pub fn slc0_check_owner(&mut self) -> SLC0_CHECK_OWNER_W<CONF1_SPEC> {
158 SLC0_CHECK_OWNER_W::new(self, 0)
159 }
160 #[doc = "Bit 1"]
161 #[inline(always)]
162 pub fn slc0_tx_check_sum_en(&mut self) -> SLC0_TX_CHECK_SUM_EN_W<CONF1_SPEC> {
163 SLC0_TX_CHECK_SUM_EN_W::new(self, 1)
164 }
165 #[doc = "Bit 2"]
166 #[inline(always)]
167 pub fn slc0_rx_check_sum_en(&mut self) -> SLC0_RX_CHECK_SUM_EN_W<CONF1_SPEC> {
168 SLC0_RX_CHECK_SUM_EN_W::new(self, 2)
169 }
170 #[doc = "Bit 3"]
171 #[inline(always)]
172 pub fn cmd_hold_en(&mut self) -> CMD_HOLD_EN_W<CONF1_SPEC> {
173 CMD_HOLD_EN_W::new(self, 3)
174 }
175 #[doc = "Bit 4"]
176 #[inline(always)]
177 pub fn slc0_len_auto_clr(&mut self) -> SLC0_LEN_AUTO_CLR_W<CONF1_SPEC> {
178 SLC0_LEN_AUTO_CLR_W::new(self, 4)
179 }
180 #[doc = "Bit 5"]
181 #[inline(always)]
182 pub fn slc0_tx_stitch_en(&mut self) -> SLC0_TX_STITCH_EN_W<CONF1_SPEC> {
183 SLC0_TX_STITCH_EN_W::new(self, 5)
184 }
185 #[doc = "Bit 6"]
186 #[inline(always)]
187 pub fn slc0_rx_stitch_en(&mut self) -> SLC0_RX_STITCH_EN_W<CONF1_SPEC> {
188 SLC0_RX_STITCH_EN_W::new(self, 6)
189 }
190 #[doc = "Bit 16"]
191 #[inline(always)]
192 pub fn slc1_check_owner(&mut self) -> SLC1_CHECK_OWNER_W<CONF1_SPEC> {
193 SLC1_CHECK_OWNER_W::new(self, 16)
194 }
195 #[doc = "Bit 17"]
196 #[inline(always)]
197 pub fn slc1_tx_check_sum_en(&mut self) -> SLC1_TX_CHECK_SUM_EN_W<CONF1_SPEC> {
198 SLC1_TX_CHECK_SUM_EN_W::new(self, 17)
199 }
200 #[doc = "Bit 18"]
201 #[inline(always)]
202 pub fn slc1_rx_check_sum_en(&mut self) -> SLC1_RX_CHECK_SUM_EN_W<CONF1_SPEC> {
203 SLC1_RX_CHECK_SUM_EN_W::new(self, 18)
204 }
205 #[doc = "Bit 19"]
206 #[inline(always)]
207 pub fn host_int_level_sel(&mut self) -> HOST_INT_LEVEL_SEL_W<CONF1_SPEC> {
208 HOST_INT_LEVEL_SEL_W::new(self, 19)
209 }
210 #[doc = "Bit 20"]
211 #[inline(always)]
212 pub fn slc1_tx_stitch_en(&mut self) -> SLC1_TX_STITCH_EN_W<CONF1_SPEC> {
213 SLC1_TX_STITCH_EN_W::new(self, 20)
214 }
215 #[doc = "Bit 21"]
216 #[inline(always)]
217 pub fn slc1_rx_stitch_en(&mut self) -> SLC1_RX_STITCH_EN_W<CONF1_SPEC> {
218 SLC1_RX_STITCH_EN_W::new(self, 21)
219 }
220 #[doc = "Bit 22"]
221 #[inline(always)]
222 pub fn clk_en(&mut self) -> CLK_EN_W<CONF1_SPEC> {
223 CLK_EN_W::new(self, 22)
224 }
225}
226#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`conf1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`conf1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
227pub struct CONF1_SPEC;
228impl crate::RegisterSpec for CONF1_SPEC {
229 type Ux = u32;
230}
231#[doc = "`read()` method returns [`conf1::R`](R) reader structure"]
232impl crate::Readable for CONF1_SPEC {}
233#[doc = "`write(|w| ..)` method takes [`conf1::W`](W) writer structure"]
234impl crate::Writable for CONF1_SPEC {
235 type Safety = crate::Unsafe;
236 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
237 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
238}
239#[doc = "`reset()` method sets CONF1 to value 0x0030_0078"]
240impl crate::Resettable for CONF1_SPEC {
241 const RESET_VALUE: u32 = 0x0030_0078;
242}