1#[doc = "Register `FIFOTH` reader"]
2pub type R = crate::R<FIFOTH_SPEC>;
3#[doc = "Register `FIFOTH` writer"]
4pub type W = crate::W<FIFOTH_SPEC>;
5#[doc = "Field `TX_WMARK` reader - FIFO threshold watermark level when transmitting data to card. When FIFO data count is less than or equal to this number, DMA/FIFO request is raised. If Interrupt is enabled, then interrupt occurs. During end of packet, request or interrupt is generated, regardless of threshold programming.In non-DMA mode, when transmit FIFO threshold (TXDR) interrupt is enabled, then interrupt is generated instead of DMA request. During end of packet, on last interrupt, host is responsible for filling FIFO with only required remaining bytes (not before FIFO is full or after CIU completes data transfers, because FIFO may not be empty). In DMA mode, at end of packet, if last transfer is less than burst size, DMA controller does single cycles until required bytes are transferred."]
6pub type TX_WMARK_R = crate::FieldReader<u16>;
7#[doc = "Field `TX_WMARK` writer - FIFO threshold watermark level when transmitting data to card. When FIFO data count is less than or equal to this number, DMA/FIFO request is raised. If Interrupt is enabled, then interrupt occurs. During end of packet, request or interrupt is generated, regardless of threshold programming.In non-DMA mode, when transmit FIFO threshold (TXDR) interrupt is enabled, then interrupt is generated instead of DMA request. During end of packet, on last interrupt, host is responsible for filling FIFO with only required remaining bytes (not before FIFO is full or after CIU completes data transfers, because FIFO may not be empty). In DMA mode, at end of packet, if last transfer is less than burst size, DMA controller does single cycles until required bytes are transferred."]
8pub type TX_WMARK_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
9#[doc = "Field `RX_WMARK` reader - FIFO threshold watermark level when receiving data to card.When FIFO data count reaches greater than this number , DMA/FIFO request is raised. During end of packet, request is generated regardless of threshold programming in order to complete any remaining data.In non-DMA mode, when receiver FIFO threshold (RXDR) interrupt is enabled, then interrupt is generated instead of DMA request.During end of packet, interrupt is not generated if threshold programming is larger than any remaining data. It is responsibility of host to read remaining bytes on seeing Data Transfer Done interrupt.In DMA mode, at end of packet, even if remaining bytes are less than threshold, DMA request does single transfers to flush out any remaining bytes before Data Transfer Done interrupt is set."]
10pub type RX_WMARK_R = crate::FieldReader<u16>;
11#[doc = "Field `RX_WMARK` writer - FIFO threshold watermark level when receiving data to card.When FIFO data count reaches greater than this number , DMA/FIFO request is raised. During end of packet, request is generated regardless of threshold programming in order to complete any remaining data.In non-DMA mode, when receiver FIFO threshold (RXDR) interrupt is enabled, then interrupt is generated instead of DMA request.During end of packet, interrupt is not generated if threshold programming is larger than any remaining data. It is responsibility of host to read remaining bytes on seeing Data Transfer Done interrupt.In DMA mode, at end of packet, even if remaining bytes are less than threshold, DMA request does single transfers to flush out any remaining bytes before Data Transfer Done interrupt is set."]
12pub type RX_WMARK_W<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>;
13#[doc = "Field `DMA_MULTIPLE_TRANSACTION_SIZE` reader - Burst size of multiple transaction, should be programmed same as DMA controller multiple-transaction-size SDHOST_SRC/DEST_MSIZE. 000: 1-byte transfer; 001: 4-byte transfer; 010: 8-byte transfer; 011: 16-byte transfer; 100: 32-byte transfer; 101: 64-byte transfer; 110: 128-byte transfer; 111: 256-byte transfer."]
14pub type DMA_MULTIPLE_TRANSACTION_SIZE_R = crate::FieldReader;
15#[doc = "Field `DMA_MULTIPLE_TRANSACTION_SIZE` writer - Burst size of multiple transaction, should be programmed same as DMA controller multiple-transaction-size SDHOST_SRC/DEST_MSIZE. 000: 1-byte transfer; 001: 4-byte transfer; 010: 8-byte transfer; 011: 16-byte transfer; 100: 32-byte transfer; 101: 64-byte transfer; 110: 128-byte transfer; 111: 256-byte transfer."]
16pub type DMA_MULTIPLE_TRANSACTION_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
17impl R {
18 #[doc = "Bits 0:11 - FIFO threshold watermark level when transmitting data to card. When FIFO data count is less than or equal to this number, DMA/FIFO request is raised. If Interrupt is enabled, then interrupt occurs. During end of packet, request or interrupt is generated, regardless of threshold programming.In non-DMA mode, when transmit FIFO threshold (TXDR) interrupt is enabled, then interrupt is generated instead of DMA request. During end of packet, on last interrupt, host is responsible for filling FIFO with only required remaining bytes (not before FIFO is full or after CIU completes data transfers, because FIFO may not be empty). In DMA mode, at end of packet, if last transfer is less than burst size, DMA controller does single cycles until required bytes are transferred."]
19 #[inline(always)]
20 pub fn tx_wmark(&self) -> TX_WMARK_R {
21 TX_WMARK_R::new((self.bits & 0x0fff) as u16)
22 }
23 #[doc = "Bits 16:26 - FIFO threshold watermark level when receiving data to card.When FIFO data count reaches greater than this number , DMA/FIFO request is raised. During end of packet, request is generated regardless of threshold programming in order to complete any remaining data.In non-DMA mode, when receiver FIFO threshold (RXDR) interrupt is enabled, then interrupt is generated instead of DMA request.During end of packet, interrupt is not generated if threshold programming is larger than any remaining data. It is responsibility of host to read remaining bytes on seeing Data Transfer Done interrupt.In DMA mode, at end of packet, even if remaining bytes are less than threshold, DMA request does single transfers to flush out any remaining bytes before Data Transfer Done interrupt is set."]
24 #[inline(always)]
25 pub fn rx_wmark(&self) -> RX_WMARK_R {
26 RX_WMARK_R::new(((self.bits >> 16) & 0x07ff) as u16)
27 }
28 #[doc = "Bits 28:30 - Burst size of multiple transaction, should be programmed same as DMA controller multiple-transaction-size SDHOST_SRC/DEST_MSIZE. 000: 1-byte transfer; 001: 4-byte transfer; 010: 8-byte transfer; 011: 16-byte transfer; 100: 32-byte transfer; 101: 64-byte transfer; 110: 128-byte transfer; 111: 256-byte transfer."]
29 #[inline(always)]
30 pub fn dma_multiple_transaction_size(&self) -> DMA_MULTIPLE_TRANSACTION_SIZE_R {
31 DMA_MULTIPLE_TRANSACTION_SIZE_R::new(((self.bits >> 28) & 7) as u8)
32 }
33}
34#[cfg(feature = "impl-register-debug")]
35impl core::fmt::Debug for R {
36 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
37 f.debug_struct("FIFOTH")
38 .field("tx_wmark", &self.tx_wmark())
39 .field("rx_wmark", &self.rx_wmark())
40 .field(
41 "dma_multiple_transaction_size",
42 &self.dma_multiple_transaction_size(),
43 )
44 .finish()
45 }
46}
47impl W {
48 #[doc = "Bits 0:11 - FIFO threshold watermark level when transmitting data to card. When FIFO data count is less than or equal to this number, DMA/FIFO request is raised. If Interrupt is enabled, then interrupt occurs. During end of packet, request or interrupt is generated, regardless of threshold programming.In non-DMA mode, when transmit FIFO threshold (TXDR) interrupt is enabled, then interrupt is generated instead of DMA request. During end of packet, on last interrupt, host is responsible for filling FIFO with only required remaining bytes (not before FIFO is full or after CIU completes data transfers, because FIFO may not be empty). In DMA mode, at end of packet, if last transfer is less than burst size, DMA controller does single cycles until required bytes are transferred."]
49 #[inline(always)]
50 pub fn tx_wmark(&mut self) -> TX_WMARK_W<FIFOTH_SPEC> {
51 TX_WMARK_W::new(self, 0)
52 }
53 #[doc = "Bits 16:26 - FIFO threshold watermark level when receiving data to card.When FIFO data count reaches greater than this number , DMA/FIFO request is raised. During end of packet, request is generated regardless of threshold programming in order to complete any remaining data.In non-DMA mode, when receiver FIFO threshold (RXDR) interrupt is enabled, then interrupt is generated instead of DMA request.During end of packet, interrupt is not generated if threshold programming is larger than any remaining data. It is responsibility of host to read remaining bytes on seeing Data Transfer Done interrupt.In DMA mode, at end of packet, even if remaining bytes are less than threshold, DMA request does single transfers to flush out any remaining bytes before Data Transfer Done interrupt is set."]
54 #[inline(always)]
55 pub fn rx_wmark(&mut self) -> RX_WMARK_W<FIFOTH_SPEC> {
56 RX_WMARK_W::new(self, 16)
57 }
58 #[doc = "Bits 28:30 - Burst size of multiple transaction, should be programmed same as DMA controller multiple-transaction-size SDHOST_SRC/DEST_MSIZE. 000: 1-byte transfer; 001: 4-byte transfer; 010: 8-byte transfer; 011: 16-byte transfer; 100: 32-byte transfer; 101: 64-byte transfer; 110: 128-byte transfer; 111: 256-byte transfer."]
59 #[inline(always)]
60 pub fn dma_multiple_transaction_size(
61 &mut self,
62 ) -> DMA_MULTIPLE_TRANSACTION_SIZE_W<FIFOTH_SPEC> {
63 DMA_MULTIPLE_TRANSACTION_SIZE_W::new(self, 28)
64 }
65}
66#[doc = "FIFO configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`fifoth::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifoth::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
67pub struct FIFOTH_SPEC;
68impl crate::RegisterSpec for FIFOTH_SPEC {
69 type Ux = u32;
70}
71#[doc = "`read()` method returns [`fifoth::R`](R) reader structure"]
72impl crate::Readable for FIFOTH_SPEC {}
73#[doc = "`write(|w| ..)` method takes [`fifoth::W`](W) writer structure"]
74impl crate::Writable for FIFOTH_SPEC {
75 type Safety = crate::Unsafe;
76 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
77 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
78}
79#[doc = "`reset()` method sets FIFOTH to value 0"]
80impl crate::Resettable for FIFOTH_SPEC {
81 const RESET_VALUE: u32 = 0;
82}