esp32/rtc_i2c/
int_clr.rs

1#[doc = "Register `INT_CLR` reader"]
2pub type R = crate::R<INT_CLR_SPEC>;
3#[doc = "Register `INT_CLR` writer"]
4pub type W = crate::W<INT_CLR_SPEC>;
5#[doc = "Field `SLAVE_TRANS_COMPLETE` reader - "]
6pub type SLAVE_TRANS_COMPLETE_R = crate::BitReader;
7#[doc = "Field `SLAVE_TRANS_COMPLETE` writer - "]
8pub type SLAVE_TRANS_COMPLETE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
9#[doc = "Field `ARBITRATION_LOST` reader - "]
10pub type ARBITRATION_LOST_R = crate::BitReader;
11#[doc = "Field `ARBITRATION_LOST` writer - "]
12pub type ARBITRATION_LOST_W<'a, REG> = crate::BitWriter1C<'a, REG>;
13#[doc = "Field `MASTER_TRANS_COMPLETE` reader - "]
14pub type MASTER_TRANS_COMPLETE_R = crate::BitReader;
15#[doc = "Field `MASTER_TRANS_COMPLETE` writer - "]
16pub type MASTER_TRANS_COMPLETE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
17#[doc = "Field `TRANS_COMPLETE` reader - "]
18pub type TRANS_COMPLETE_R = crate::BitReader;
19#[doc = "Field `TRANS_COMPLETE` writer - "]
20pub type TRANS_COMPLETE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
21#[doc = "Field `TIME_OUT` writer - "]
22pub type TIME_OUT_W<'a, REG> = crate::BitWriter1C<'a, REG>;
23impl R {
24    #[doc = "Bit 4"]
25    #[inline(always)]
26    pub fn slave_trans_complete(&self) -> SLAVE_TRANS_COMPLETE_R {
27        SLAVE_TRANS_COMPLETE_R::new(((self.bits >> 4) & 1) != 0)
28    }
29    #[doc = "Bit 5"]
30    #[inline(always)]
31    pub fn arbitration_lost(&self) -> ARBITRATION_LOST_R {
32        ARBITRATION_LOST_R::new(((self.bits >> 5) & 1) != 0)
33    }
34    #[doc = "Bit 6"]
35    #[inline(always)]
36    pub fn master_trans_complete(&self) -> MASTER_TRANS_COMPLETE_R {
37        MASTER_TRANS_COMPLETE_R::new(((self.bits >> 6) & 1) != 0)
38    }
39    #[doc = "Bit 7"]
40    #[inline(always)]
41    pub fn trans_complete(&self) -> TRANS_COMPLETE_R {
42        TRANS_COMPLETE_R::new(((self.bits >> 7) & 1) != 0)
43    }
44}
45#[cfg(feature = "impl-register-debug")]
46impl core::fmt::Debug for R {
47    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
48        f.debug_struct("INT_CLR")
49            .field("slave_trans_complete", &self.slave_trans_complete())
50            .field("arbitration_lost", &self.arbitration_lost())
51            .field("master_trans_complete", &self.master_trans_complete())
52            .field("trans_complete", &self.trans_complete())
53            .finish()
54    }
55}
56impl W {
57    #[doc = "Bit 4"]
58    #[inline(always)]
59    pub fn slave_trans_complete(&mut self) -> SLAVE_TRANS_COMPLETE_W<INT_CLR_SPEC> {
60        SLAVE_TRANS_COMPLETE_W::new(self, 4)
61    }
62    #[doc = "Bit 5"]
63    #[inline(always)]
64    pub fn arbitration_lost(&mut self) -> ARBITRATION_LOST_W<INT_CLR_SPEC> {
65        ARBITRATION_LOST_W::new(self, 5)
66    }
67    #[doc = "Bit 6"]
68    #[inline(always)]
69    pub fn master_trans_complete(&mut self) -> MASTER_TRANS_COMPLETE_W<INT_CLR_SPEC> {
70        MASTER_TRANS_COMPLETE_W::new(self, 6)
71    }
72    #[doc = "Bit 7"]
73    #[inline(always)]
74    pub fn trans_complete(&mut self) -> TRANS_COMPLETE_W<INT_CLR_SPEC> {
75        TRANS_COMPLETE_W::new(self, 7)
76    }
77    #[doc = "Bit 8"]
78    #[inline(always)]
79    pub fn time_out(&mut self) -> TIME_OUT_W<INT_CLR_SPEC> {
80        TIME_OUT_W::new(self, 8)
81    }
82}
83#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`int_clr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
84pub struct INT_CLR_SPEC;
85impl crate::RegisterSpec for INT_CLR_SPEC {
86    type Ux = u32;
87}
88#[doc = "`read()` method returns [`int_clr::R`](R) reader structure"]
89impl crate::Readable for INT_CLR_SPEC {}
90#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"]
91impl crate::Writable for INT_CLR_SPEC {
92    type Safety = crate::Unsafe;
93    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
94    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x01f0;
95}
96#[doc = "`reset()` method sets INT_CLR to value 0"]
97impl crate::Resettable for INT_CLR_SPEC {
98    const RESET_VALUE: u32 = 0;
99}
esp32/rtc_i2c/int_clr.rs

esp32/rtc_i2c/
int_clr.rs
