esp32/dport/
pro_cache_ctrl1.rs

1#[doc = "Register `PRO_CACHE_CTRL1` reader"]
2pub type R = crate::R<PRO_CACHE_CTRL1_SPEC>;
3#[doc = "Register `PRO_CACHE_CTRL1` writer"]
4pub type W = crate::W<PRO_CACHE_CTRL1_SPEC>;
5#[doc = "Field `PRO_CACHE_MASK_IRAM0` reader - "]
6pub type PRO_CACHE_MASK_IRAM0_R = crate::BitReader;
7#[doc = "Field `PRO_CACHE_MASK_IRAM0` writer - "]
8pub type PRO_CACHE_MASK_IRAM0_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `PRO_CACHE_MASK_IRAM1` reader - "]
10pub type PRO_CACHE_MASK_IRAM1_R = crate::BitReader;
11#[doc = "Field `PRO_CACHE_MASK_IRAM1` writer - "]
12pub type PRO_CACHE_MASK_IRAM1_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `PRO_CACHE_MASK_IROM0` reader - "]
14pub type PRO_CACHE_MASK_IROM0_R = crate::BitReader;
15#[doc = "Field `PRO_CACHE_MASK_IROM0` writer - "]
16pub type PRO_CACHE_MASK_IROM0_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `PRO_CACHE_MASK_DRAM1` reader - "]
18pub type PRO_CACHE_MASK_DRAM1_R = crate::BitReader;
19#[doc = "Field `PRO_CACHE_MASK_DRAM1` writer - "]
20pub type PRO_CACHE_MASK_DRAM1_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `PRO_CACHE_MASK_DROM0` reader - "]
22pub type PRO_CACHE_MASK_DROM0_R = crate::BitReader;
23#[doc = "Field `PRO_CACHE_MASK_DROM0` writer - "]
24pub type PRO_CACHE_MASK_DROM0_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `PRO_CACHE_MASK_OPSDRAM` reader - "]
26pub type PRO_CACHE_MASK_OPSDRAM_R = crate::BitReader;
27#[doc = "Field `PRO_CACHE_MASK_OPSDRAM` writer - "]
28pub type PRO_CACHE_MASK_OPSDRAM_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `PRO_CMMU_SRAM_PAGE_MODE` reader - "]
30pub type PRO_CMMU_SRAM_PAGE_MODE_R = crate::FieldReader;
31#[doc = "Field `PRO_CMMU_SRAM_PAGE_MODE` writer - "]
32pub type PRO_CMMU_SRAM_PAGE_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
33#[doc = "Field `PRO_CMMU_FLASH_PAGE_MODE` reader - "]
34pub type PRO_CMMU_FLASH_PAGE_MODE_R = crate::FieldReader;
35#[doc = "Field `PRO_CMMU_FLASH_PAGE_MODE` writer - "]
36pub type PRO_CMMU_FLASH_PAGE_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
37#[doc = "Field `PRO_CMMU_FORCE_ON` reader - "]
38pub type PRO_CMMU_FORCE_ON_R = crate::BitReader;
39#[doc = "Field `PRO_CMMU_FORCE_ON` writer - "]
40pub type PRO_CMMU_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `PRO_CMMU_PD` reader - "]
42pub type PRO_CMMU_PD_R = crate::BitReader;
43#[doc = "Field `PRO_CMMU_PD` writer - "]
44pub type PRO_CMMU_PD_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `PRO_CACHE_MMU_IA_CLR` reader - "]
46pub type PRO_CACHE_MMU_IA_CLR_R = crate::BitReader;
47#[doc = "Field `PRO_CACHE_MMU_IA_CLR` writer - "]
48pub type PRO_CACHE_MMU_IA_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
49impl R {
50    #[doc = "Bit 0"]
51    #[inline(always)]
52    pub fn pro_cache_mask_iram0(&self) -> PRO_CACHE_MASK_IRAM0_R {
53        PRO_CACHE_MASK_IRAM0_R::new((self.bits & 1) != 0)
54    }
55    #[doc = "Bit 1"]
56    #[inline(always)]
57    pub fn pro_cache_mask_iram1(&self) -> PRO_CACHE_MASK_IRAM1_R {
58        PRO_CACHE_MASK_IRAM1_R::new(((self.bits >> 1) & 1) != 0)
59    }
60    #[doc = "Bit 2"]
61    #[inline(always)]
62    pub fn pro_cache_mask_irom0(&self) -> PRO_CACHE_MASK_IROM0_R {
63        PRO_CACHE_MASK_IROM0_R::new(((self.bits >> 2) & 1) != 0)
64    }
65    #[doc = "Bit 3"]
66    #[inline(always)]
67    pub fn pro_cache_mask_dram1(&self) -> PRO_CACHE_MASK_DRAM1_R {
68        PRO_CACHE_MASK_DRAM1_R::new(((self.bits >> 3) & 1) != 0)
69    }
70    #[doc = "Bit 4"]
71    #[inline(always)]
72    pub fn pro_cache_mask_drom0(&self) -> PRO_CACHE_MASK_DROM0_R {
73        PRO_CACHE_MASK_DROM0_R::new(((self.bits >> 4) & 1) != 0)
74    }
75    #[doc = "Bit 5"]
76    #[inline(always)]
77    pub fn pro_cache_mask_opsdram(&self) -> PRO_CACHE_MASK_OPSDRAM_R {
78        PRO_CACHE_MASK_OPSDRAM_R::new(((self.bits >> 5) & 1) != 0)
79    }
80    #[doc = "Bits 6:8"]
81    #[inline(always)]
82    pub fn pro_cmmu_sram_page_mode(&self) -> PRO_CMMU_SRAM_PAGE_MODE_R {
83        PRO_CMMU_SRAM_PAGE_MODE_R::new(((self.bits >> 6) & 7) as u8)
84    }
85    #[doc = "Bits 9:10"]
86    #[inline(always)]
87    pub fn pro_cmmu_flash_page_mode(&self) -> PRO_CMMU_FLASH_PAGE_MODE_R {
88        PRO_CMMU_FLASH_PAGE_MODE_R::new(((self.bits >> 9) & 3) as u8)
89    }
90    #[doc = "Bit 11"]
91    #[inline(always)]
92    pub fn pro_cmmu_force_on(&self) -> PRO_CMMU_FORCE_ON_R {
93        PRO_CMMU_FORCE_ON_R::new(((self.bits >> 11) & 1) != 0)
94    }
95    #[doc = "Bit 12"]
96    #[inline(always)]
97    pub fn pro_cmmu_pd(&self) -> PRO_CMMU_PD_R {
98        PRO_CMMU_PD_R::new(((self.bits >> 12) & 1) != 0)
99    }
100    #[doc = "Bit 13"]
101    #[inline(always)]
102    pub fn pro_cache_mmu_ia_clr(&self) -> PRO_CACHE_MMU_IA_CLR_R {
103        PRO_CACHE_MMU_IA_CLR_R::new(((self.bits >> 13) & 1) != 0)
104    }
105}
106#[cfg(feature = "impl-register-debug")]
107impl core::fmt::Debug for R {
108    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
109        f.debug_struct("PRO_CACHE_CTRL1")
110            .field("pro_cache_mask_iram0", &self.pro_cache_mask_iram0())
111            .field("pro_cache_mask_iram1", &self.pro_cache_mask_iram1())
112            .field("pro_cache_mask_irom0", &self.pro_cache_mask_irom0())
113            .field("pro_cache_mask_dram1", &self.pro_cache_mask_dram1())
114            .field("pro_cache_mask_drom0", &self.pro_cache_mask_drom0())
115            .field("pro_cache_mask_opsdram", &self.pro_cache_mask_opsdram())
116            .field("pro_cmmu_sram_page_mode", &self.pro_cmmu_sram_page_mode())
117            .field("pro_cmmu_flash_page_mode", &self.pro_cmmu_flash_page_mode())
118            .field("pro_cmmu_force_on", &self.pro_cmmu_force_on())
119            .field("pro_cmmu_pd", &self.pro_cmmu_pd())
120            .field("pro_cache_mmu_ia_clr", &self.pro_cache_mmu_ia_clr())
121            .finish()
122    }
123}
124impl W {
125    #[doc = "Bit 0"]
126    #[inline(always)]
127    pub fn pro_cache_mask_iram0(&mut self) -> PRO_CACHE_MASK_IRAM0_W<PRO_CACHE_CTRL1_SPEC> {
128        PRO_CACHE_MASK_IRAM0_W::new(self, 0)
129    }
130    #[doc = "Bit 1"]
131    #[inline(always)]
132    pub fn pro_cache_mask_iram1(&mut self) -> PRO_CACHE_MASK_IRAM1_W<PRO_CACHE_CTRL1_SPEC> {
133        PRO_CACHE_MASK_IRAM1_W::new(self, 1)
134    }
135    #[doc = "Bit 2"]
136    #[inline(always)]
137    pub fn pro_cache_mask_irom0(&mut self) -> PRO_CACHE_MASK_IROM0_W<PRO_CACHE_CTRL1_SPEC> {
138        PRO_CACHE_MASK_IROM0_W::new(self, 2)
139    }
140    #[doc = "Bit 3"]
141    #[inline(always)]
142    pub fn pro_cache_mask_dram1(&mut self) -> PRO_CACHE_MASK_DRAM1_W<PRO_CACHE_CTRL1_SPEC> {
143        PRO_CACHE_MASK_DRAM1_W::new(self, 3)
144    }
145    #[doc = "Bit 4"]
146    #[inline(always)]
147    pub fn pro_cache_mask_drom0(&mut self) -> PRO_CACHE_MASK_DROM0_W<PRO_CACHE_CTRL1_SPEC> {
148        PRO_CACHE_MASK_DROM0_W::new(self, 4)
149    }
150    #[doc = "Bit 5"]
151    #[inline(always)]
152    pub fn pro_cache_mask_opsdram(&mut self) -> PRO_CACHE_MASK_OPSDRAM_W<PRO_CACHE_CTRL1_SPEC> {
153        PRO_CACHE_MASK_OPSDRAM_W::new(self, 5)
154    }
155    #[doc = "Bits 6:8"]
156    #[inline(always)]
157    pub fn pro_cmmu_sram_page_mode(&mut self) -> PRO_CMMU_SRAM_PAGE_MODE_W<PRO_CACHE_CTRL1_SPEC> {
158        PRO_CMMU_SRAM_PAGE_MODE_W::new(self, 6)
159    }
160    #[doc = "Bits 9:10"]
161    #[inline(always)]
162    pub fn pro_cmmu_flash_page_mode(&mut self) -> PRO_CMMU_FLASH_PAGE_MODE_W<PRO_CACHE_CTRL1_SPEC> {
163        PRO_CMMU_FLASH_PAGE_MODE_W::new(self, 9)
164    }
165    #[doc = "Bit 11"]
166    #[inline(always)]
167    pub fn pro_cmmu_force_on(&mut self) -> PRO_CMMU_FORCE_ON_W<PRO_CACHE_CTRL1_SPEC> {
168        PRO_CMMU_FORCE_ON_W::new(self, 11)
169    }
170    #[doc = "Bit 12"]
171    #[inline(always)]
172    pub fn pro_cmmu_pd(&mut self) -> PRO_CMMU_PD_W<PRO_CACHE_CTRL1_SPEC> {
173        PRO_CMMU_PD_W::new(self, 12)
174    }
175    #[doc = "Bit 13"]
176    #[inline(always)]
177    pub fn pro_cache_mmu_ia_clr(&mut self) -> PRO_CACHE_MMU_IA_CLR_W<PRO_CACHE_CTRL1_SPEC> {
178        PRO_CACHE_MMU_IA_CLR_W::new(self, 13)
179    }
180}
181#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`pro_cache_ctrl1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pro_cache_ctrl1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
182pub struct PRO_CACHE_CTRL1_SPEC;
183impl crate::RegisterSpec for PRO_CACHE_CTRL1_SPEC {
184    type Ux = u32;
185}
186#[doc = "`read()` method returns [`pro_cache_ctrl1::R`](R) reader structure"]
187impl crate::Readable for PRO_CACHE_CTRL1_SPEC {}
188#[doc = "`write(|w| ..)` method takes [`pro_cache_ctrl1::W`](W) writer structure"]
189impl crate::Writable for PRO_CACHE_CTRL1_SPEC {
190    type Safety = crate::Unsafe;
191    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
192    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
193}
194#[doc = "`reset()` method sets PRO_CACHE_CTRL1 to value 0x08ff"]
195impl crate::Resettable for PRO_CACHE_CTRL1_SPEC {
196    const RESET_VALUE: u32 = 0x08ff;
197}
esp32/dport/pro_cache_ctrl1.rs

esp32/dport/
pro_cache_ctrl1.rs
