1#[doc = "Register `CONF0` reader"]
2pub type R = crate::R<CONF0_SPEC>;
3#[doc = "Register `CONF0` writer"]
4pub type W = crate::W<CONF0_SPEC>;
5#[doc = "Field `PARITY` reader - This register is used to configure the parity check mode. 0:even 1:odd"]
6pub type PARITY_R = crate::BitReader;
7#[doc = "Field `PARITY` writer - This register is used to configure the parity check mode. 0:even 1:odd"]
8pub type PARITY_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `PARITY_EN` reader - Set this bit to enable uart parity check."]
10pub type PARITY_EN_R = crate::BitReader;
11#[doc = "Field `PARITY_EN` writer - Set this bit to enable uart parity check."]
12pub type PARITY_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `BIT_NUM` reader - This registe is used to set the length of data: 0:5bits 1:6bits 2:7bits 3:8bits"]
14pub type BIT_NUM_R = crate::FieldReader;
15#[doc = "Field `BIT_NUM` writer - This registe is used to set the length of data: 0:5bits 1:6bits 2:7bits 3:8bits"]
16pub type BIT_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
17#[doc = "Field `STOP_BIT_NUM` reader - This register is used to set the length of stop bit. 1:1bit 2:1.5bits 3:2bits"]
18pub type STOP_BIT_NUM_R = crate::FieldReader;
19#[doc = "Field `STOP_BIT_NUM` writer - This register is used to set the length of stop bit. 1:1bit 2:1.5bits 3:2bits"]
20pub type STOP_BIT_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
21#[doc = "Field `SW_RTS` reader - This register is used to configure the software rts signal which is used in software flow control."]
22pub type SW_RTS_R = crate::BitReader;
23#[doc = "Field `SW_RTS` writer - This register is used to configure the software rts signal which is used in software flow control."]
24pub type SW_RTS_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `SW_DTR` reader - This register is used to configure the software dtr signal which is used in software flow control.."]
26pub type SW_DTR_R = crate::BitReader;
27#[doc = "Field `SW_DTR` writer - This register is used to configure the software dtr signal which is used in software flow control.."]
28pub type SW_DTR_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `TXD_BRK` reader - Set this bit to enbale transmitter to send 0 when the process of sending data is done."]
30pub type TXD_BRK_R = crate::BitReader;
31#[doc = "Field `TXD_BRK` writer - Set this bit to enbale transmitter to send 0 when the process of sending data is done."]
32pub type TXD_BRK_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `IRDA_DPLX` reader - Set this bit to enable irda loopback mode."]
34pub type IRDA_DPLX_R = crate::BitReader;
35#[doc = "Field `IRDA_DPLX` writer - Set this bit to enable irda loopback mode."]
36pub type IRDA_DPLX_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `IRDA_TX_EN` reader - This is the start enable bit for irda transmitter."]
38pub type IRDA_TX_EN_R = crate::BitReader;
39#[doc = "Field `IRDA_TX_EN` writer - This is the start enable bit for irda transmitter."]
40pub type IRDA_TX_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `IRDA_WCTL` reader - 1.the irda transmitter's 11th bit is the same to the 10th bit. 0.set irda transmitter's 11th bit to 0."]
42pub type IRDA_WCTL_R = crate::BitReader;
43#[doc = "Field `IRDA_WCTL` writer - 1.the irda transmitter's 11th bit is the same to the 10th bit. 0.set irda transmitter's 11th bit to 0."]
44pub type IRDA_WCTL_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `IRDA_TX_INV` reader - Set this bit to inverse the level value of irda transmitter's level."]
46pub type IRDA_TX_INV_R = crate::BitReader;
47#[doc = "Field `IRDA_TX_INV` writer - Set this bit to inverse the level value of irda transmitter's level."]
48pub type IRDA_TX_INV_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `IRDA_RX_INV` reader - Set this bit to inverse the level value of irda receiver's level."]
50pub type IRDA_RX_INV_R = crate::BitReader;
51#[doc = "Field `IRDA_RX_INV` writer - Set this bit to inverse the level value of irda receiver's level."]
52pub type IRDA_RX_INV_W<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `LOOPBACK` reader - Set this bit to enable uart loopback test mode."]
54pub type LOOPBACK_R = crate::BitReader;
55#[doc = "Field `LOOPBACK` writer - Set this bit to enable uart loopback test mode."]
56pub type LOOPBACK_W<'a, REG> = crate::BitWriter<'a, REG>;
57#[doc = "Field `TX_FLOW_EN` reader - Set this bit to enable transmitter's flow control function."]
58pub type TX_FLOW_EN_R = crate::BitReader;
59#[doc = "Field `TX_FLOW_EN` writer - Set this bit to enable transmitter's flow control function."]
60pub type TX_FLOW_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
61#[doc = "Field `IRDA_EN` reader - Set this bit to enable irda protocol."]
62pub type IRDA_EN_R = crate::BitReader;
63#[doc = "Field `IRDA_EN` writer - Set this bit to enable irda protocol."]
64pub type IRDA_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
65#[doc = "Field `RXFIFO_RST` reader - Set this bit to reset uart receiver's fifo."]
66pub type RXFIFO_RST_R = crate::BitReader;
67#[doc = "Field `RXFIFO_RST` writer - Set this bit to reset uart receiver's fifo."]
68pub type RXFIFO_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
69#[doc = "Field `TXFIFO_RST` reader - Set this bit to reset uart transmitter's fifo."]
70pub type TXFIFO_RST_R = crate::BitReader;
71#[doc = "Field `TXFIFO_RST` writer - Set this bit to reset uart transmitter's fifo."]
72pub type TXFIFO_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
73#[doc = "Field `RXD_INV` reader - Set this bit to inverse the level value of uart rxd signal."]
74pub type RXD_INV_R = crate::BitReader;
75#[doc = "Field `RXD_INV` writer - Set this bit to inverse the level value of uart rxd signal."]
76pub type RXD_INV_W<'a, REG> = crate::BitWriter<'a, REG>;
77#[doc = "Field `CTS_INV` reader - Set this bit to inverse the level value of uart cts signal."]
78pub type CTS_INV_R = crate::BitReader;
79#[doc = "Field `CTS_INV` writer - Set this bit to inverse the level value of uart cts signal."]
80pub type CTS_INV_W<'a, REG> = crate::BitWriter<'a, REG>;
81#[doc = "Field `DSR_INV` reader - Set this bit to inverse the level value of uart dsr signal."]
82pub type DSR_INV_R = crate::BitReader;
83#[doc = "Field `DSR_INV` writer - Set this bit to inverse the level value of uart dsr signal."]
84pub type DSR_INV_W<'a, REG> = crate::BitWriter<'a, REG>;
85#[doc = "Field `TXD_INV` reader - Set this bit to inverse the level value of uart txd signal."]
86pub type TXD_INV_R = crate::BitReader;
87#[doc = "Field `TXD_INV` writer - Set this bit to inverse the level value of uart txd signal."]
88pub type TXD_INV_W<'a, REG> = crate::BitWriter<'a, REG>;
89#[doc = "Field `RTS_INV` reader - Set this bit to inverse the level value of uart rts signal."]
90pub type RTS_INV_R = crate::BitReader;
91#[doc = "Field `RTS_INV` writer - Set this bit to inverse the level value of uart rts signal."]
92pub type RTS_INV_W<'a, REG> = crate::BitWriter<'a, REG>;
93#[doc = "Field `DTR_INV` reader - Set this bit to inverse the level value of uart dtr signal."]
94pub type DTR_INV_R = crate::BitReader;
95#[doc = "Field `DTR_INV` writer - Set this bit to inverse the level value of uart dtr signal."]
96pub type DTR_INV_W<'a, REG> = crate::BitWriter<'a, REG>;
97#[doc = "Field `CLK_EN` reader - 1.force clock on for registers.support clock only when write registers"]
98pub type CLK_EN_R = crate::BitReader;
99#[doc = "Field `CLK_EN` writer - 1.force clock on for registers.support clock only when write registers"]
100pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
101#[doc = "Field `ERR_WR_MASK` reader - 1.receiver stops storing data int fifo when data is wrong. 0.receiver stores the data even if the received data is wrong."]
102pub type ERR_WR_MASK_R = crate::BitReader;
103#[doc = "Field `ERR_WR_MASK` writer - 1.receiver stops storing data int fifo when data is wrong. 0.receiver stores the data even if the received data is wrong."]
104pub type ERR_WR_MASK_W<'a, REG> = crate::BitWriter<'a, REG>;
105#[doc = "Field `TICK_REF_ALWAYS_ON` reader - This register is used to select the clock.1.apb clock 0:ref_tick"]
106pub type TICK_REF_ALWAYS_ON_R = crate::BitReader;
107#[doc = "Field `TICK_REF_ALWAYS_ON` writer - This register is used to select the clock.1.apb clock 0:ref_tick"]
108pub type TICK_REF_ALWAYS_ON_W<'a, REG> = crate::BitWriter<'a, REG>;
109impl R {
110 #[doc = "Bit 0 - This register is used to configure the parity check mode. 0:even 1:odd"]
111 #[inline(always)]
112 pub fn parity(&self) -> PARITY_R {
113 PARITY_R::new((self.bits & 1) != 0)
114 }
115 #[doc = "Bit 1 - Set this bit to enable uart parity check."]
116 #[inline(always)]
117 pub fn parity_en(&self) -> PARITY_EN_R {
118 PARITY_EN_R::new(((self.bits >> 1) & 1) != 0)
119 }
120 #[doc = "Bits 2:3 - This registe is used to set the length of data: 0:5bits 1:6bits 2:7bits 3:8bits"]
121 #[inline(always)]
122 pub fn bit_num(&self) -> BIT_NUM_R {
123 BIT_NUM_R::new(((self.bits >> 2) & 3) as u8)
124 }
125 #[doc = "Bits 4:5 - This register is used to set the length of stop bit. 1:1bit 2:1.5bits 3:2bits"]
126 #[inline(always)]
127 pub fn stop_bit_num(&self) -> STOP_BIT_NUM_R {
128 STOP_BIT_NUM_R::new(((self.bits >> 4) & 3) as u8)
129 }
130 #[doc = "Bit 6 - This register is used to configure the software rts signal which is used in software flow control."]
131 #[inline(always)]
132 pub fn sw_rts(&self) -> SW_RTS_R {
133 SW_RTS_R::new(((self.bits >> 6) & 1) != 0)
134 }
135 #[doc = "Bit 7 - This register is used to configure the software dtr signal which is used in software flow control.."]
136 #[inline(always)]
137 pub fn sw_dtr(&self) -> SW_DTR_R {
138 SW_DTR_R::new(((self.bits >> 7) & 1) != 0)
139 }
140 #[doc = "Bit 8 - Set this bit to enbale transmitter to send 0 when the process of sending data is done."]
141 #[inline(always)]
142 pub fn txd_brk(&self) -> TXD_BRK_R {
143 TXD_BRK_R::new(((self.bits >> 8) & 1) != 0)
144 }
145 #[doc = "Bit 9 - Set this bit to enable irda loopback mode."]
146 #[inline(always)]
147 pub fn irda_dplx(&self) -> IRDA_DPLX_R {
148 IRDA_DPLX_R::new(((self.bits >> 9) & 1) != 0)
149 }
150 #[doc = "Bit 10 - This is the start enable bit for irda transmitter."]
151 #[inline(always)]
152 pub fn irda_tx_en(&self) -> IRDA_TX_EN_R {
153 IRDA_TX_EN_R::new(((self.bits >> 10) & 1) != 0)
154 }
155 #[doc = "Bit 11 - 1.the irda transmitter's 11th bit is the same to the 10th bit. 0.set irda transmitter's 11th bit to 0."]
156 #[inline(always)]
157 pub fn irda_wctl(&self) -> IRDA_WCTL_R {
158 IRDA_WCTL_R::new(((self.bits >> 11) & 1) != 0)
159 }
160 #[doc = "Bit 12 - Set this bit to inverse the level value of irda transmitter's level."]
161 #[inline(always)]
162 pub fn irda_tx_inv(&self) -> IRDA_TX_INV_R {
163 IRDA_TX_INV_R::new(((self.bits >> 12) & 1) != 0)
164 }
165 #[doc = "Bit 13 - Set this bit to inverse the level value of irda receiver's level."]
166 #[inline(always)]
167 pub fn irda_rx_inv(&self) -> IRDA_RX_INV_R {
168 IRDA_RX_INV_R::new(((self.bits >> 13) & 1) != 0)
169 }
170 #[doc = "Bit 14 - Set this bit to enable uart loopback test mode."]
171 #[inline(always)]
172 pub fn loopback(&self) -> LOOPBACK_R {
173 LOOPBACK_R::new(((self.bits >> 14) & 1) != 0)
174 }
175 #[doc = "Bit 15 - Set this bit to enable transmitter's flow control function."]
176 #[inline(always)]
177 pub fn tx_flow_en(&self) -> TX_FLOW_EN_R {
178 TX_FLOW_EN_R::new(((self.bits >> 15) & 1) != 0)
179 }
180 #[doc = "Bit 16 - Set this bit to enable irda protocol."]
181 #[inline(always)]
182 pub fn irda_en(&self) -> IRDA_EN_R {
183 IRDA_EN_R::new(((self.bits >> 16) & 1) != 0)
184 }
185 #[doc = "Bit 17 - Set this bit to reset uart receiver's fifo."]
186 #[inline(always)]
187 pub fn rxfifo_rst(&self) -> RXFIFO_RST_R {
188 RXFIFO_RST_R::new(((self.bits >> 17) & 1) != 0)
189 }
190 #[doc = "Bit 18 - Set this bit to reset uart transmitter's fifo."]
191 #[inline(always)]
192 pub fn txfifo_rst(&self) -> TXFIFO_RST_R {
193 TXFIFO_RST_R::new(((self.bits >> 18) & 1) != 0)
194 }
195 #[doc = "Bit 19 - Set this bit to inverse the level value of uart rxd signal."]
196 #[inline(always)]
197 pub fn rxd_inv(&self) -> RXD_INV_R {
198 RXD_INV_R::new(((self.bits >> 19) & 1) != 0)
199 }
200 #[doc = "Bit 20 - Set this bit to inverse the level value of uart cts signal."]
201 #[inline(always)]
202 pub fn cts_inv(&self) -> CTS_INV_R {
203 CTS_INV_R::new(((self.bits >> 20) & 1) != 0)
204 }
205 #[doc = "Bit 21 - Set this bit to inverse the level value of uart dsr signal."]
206 #[inline(always)]
207 pub fn dsr_inv(&self) -> DSR_INV_R {
208 DSR_INV_R::new(((self.bits >> 21) & 1) != 0)
209 }
210 #[doc = "Bit 22 - Set this bit to inverse the level value of uart txd signal."]
211 #[inline(always)]
212 pub fn txd_inv(&self) -> TXD_INV_R {
213 TXD_INV_R::new(((self.bits >> 22) & 1) != 0)
214 }
215 #[doc = "Bit 23 - Set this bit to inverse the level value of uart rts signal."]
216 #[inline(always)]
217 pub fn rts_inv(&self) -> RTS_INV_R {
218 RTS_INV_R::new(((self.bits >> 23) & 1) != 0)
219 }
220 #[doc = "Bit 24 - Set this bit to inverse the level value of uart dtr signal."]
221 #[inline(always)]
222 pub fn dtr_inv(&self) -> DTR_INV_R {
223 DTR_INV_R::new(((self.bits >> 24) & 1) != 0)
224 }
225 #[doc = "Bit 25 - 1.force clock on for registers.support clock only when write registers"]
226 #[inline(always)]
227 pub fn clk_en(&self) -> CLK_EN_R {
228 CLK_EN_R::new(((self.bits >> 25) & 1) != 0)
229 }
230 #[doc = "Bit 26 - 1.receiver stops storing data int fifo when data is wrong. 0.receiver stores the data even if the received data is wrong."]
231 #[inline(always)]
232 pub fn err_wr_mask(&self) -> ERR_WR_MASK_R {
233 ERR_WR_MASK_R::new(((self.bits >> 26) & 1) != 0)
234 }
235 #[doc = "Bit 27 - This register is used to select the clock.1.apb clock 0:ref_tick"]
236 #[inline(always)]
237 pub fn tick_ref_always_on(&self) -> TICK_REF_ALWAYS_ON_R {
238 TICK_REF_ALWAYS_ON_R::new(((self.bits >> 27) & 1) != 0)
239 }
240}
241#[cfg(feature = "impl-register-debug")]
242impl core::fmt::Debug for R {
243 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
244 f.debug_struct("CONF0")
245 .field("parity", &self.parity())
246 .field("parity_en", &self.parity_en())
247 .field("bit_num", &self.bit_num())
248 .field("stop_bit_num", &self.stop_bit_num())
249 .field("sw_rts", &self.sw_rts())
250 .field("sw_dtr", &self.sw_dtr())
251 .field("txd_brk", &self.txd_brk())
252 .field("irda_dplx", &self.irda_dplx())
253 .field("irda_tx_en", &self.irda_tx_en())
254 .field("irda_wctl", &self.irda_wctl())
255 .field("irda_tx_inv", &self.irda_tx_inv())
256 .field("irda_rx_inv", &self.irda_rx_inv())
257 .field("loopback", &self.loopback())
258 .field("tx_flow_en", &self.tx_flow_en())
259 .field("irda_en", &self.irda_en())
260 .field("rxfifo_rst", &self.rxfifo_rst())
261 .field("txfifo_rst", &self.txfifo_rst())
262 .field("rxd_inv", &self.rxd_inv())
263 .field("cts_inv", &self.cts_inv())
264 .field("dsr_inv", &self.dsr_inv())
265 .field("txd_inv", &self.txd_inv())
266 .field("rts_inv", &self.rts_inv())
267 .field("dtr_inv", &self.dtr_inv())
268 .field("clk_en", &self.clk_en())
269 .field("err_wr_mask", &self.err_wr_mask())
270 .field("tick_ref_always_on", &self.tick_ref_always_on())
271 .finish()
272 }
273}
274impl W {
275 #[doc = "Bit 0 - This register is used to configure the parity check mode. 0:even 1:odd"]
276 #[inline(always)]
277 pub fn parity(&mut self) -> PARITY_W<CONF0_SPEC> {
278 PARITY_W::new(self, 0)
279 }
280 #[doc = "Bit 1 - Set this bit to enable uart parity check."]
281 #[inline(always)]
282 pub fn parity_en(&mut self) -> PARITY_EN_W<CONF0_SPEC> {
283 PARITY_EN_W::new(self, 1)
284 }
285 #[doc = "Bits 2:3 - This registe is used to set the length of data: 0:5bits 1:6bits 2:7bits 3:8bits"]
286 #[inline(always)]
287 pub fn bit_num(&mut self) -> BIT_NUM_W<CONF0_SPEC> {
288 BIT_NUM_W::new(self, 2)
289 }
290 #[doc = "Bits 4:5 - This register is used to set the length of stop bit. 1:1bit 2:1.5bits 3:2bits"]
291 #[inline(always)]
292 pub fn stop_bit_num(&mut self) -> STOP_BIT_NUM_W<CONF0_SPEC> {
293 STOP_BIT_NUM_W::new(self, 4)
294 }
295 #[doc = "Bit 6 - This register is used to configure the software rts signal which is used in software flow control."]
296 #[inline(always)]
297 pub fn sw_rts(&mut self) -> SW_RTS_W<CONF0_SPEC> {
298 SW_RTS_W::new(self, 6)
299 }
300 #[doc = "Bit 7 - This register is used to configure the software dtr signal which is used in software flow control.."]
301 #[inline(always)]
302 pub fn sw_dtr(&mut self) -> SW_DTR_W<CONF0_SPEC> {
303 SW_DTR_W::new(self, 7)
304 }
305 #[doc = "Bit 8 - Set this bit to enbale transmitter to send 0 when the process of sending data is done."]
306 #[inline(always)]
307 pub fn txd_brk(&mut self) -> TXD_BRK_W<CONF0_SPEC> {
308 TXD_BRK_W::new(self, 8)
309 }
310 #[doc = "Bit 9 - Set this bit to enable irda loopback mode."]
311 #[inline(always)]
312 pub fn irda_dplx(&mut self) -> IRDA_DPLX_W<CONF0_SPEC> {
313 IRDA_DPLX_W::new(self, 9)
314 }
315 #[doc = "Bit 10 - This is the start enable bit for irda transmitter."]
316 #[inline(always)]
317 pub fn irda_tx_en(&mut self) -> IRDA_TX_EN_W<CONF0_SPEC> {
318 IRDA_TX_EN_W::new(self, 10)
319 }
320 #[doc = "Bit 11 - 1.the irda transmitter's 11th bit is the same to the 10th bit. 0.set irda transmitter's 11th bit to 0."]
321 #[inline(always)]
322 pub fn irda_wctl(&mut self) -> IRDA_WCTL_W<CONF0_SPEC> {
323 IRDA_WCTL_W::new(self, 11)
324 }
325 #[doc = "Bit 12 - Set this bit to inverse the level value of irda transmitter's level."]
326 #[inline(always)]
327 pub fn irda_tx_inv(&mut self) -> IRDA_TX_INV_W<CONF0_SPEC> {
328 IRDA_TX_INV_W::new(self, 12)
329 }
330 #[doc = "Bit 13 - Set this bit to inverse the level value of irda receiver's level."]
331 #[inline(always)]
332 pub fn irda_rx_inv(&mut self) -> IRDA_RX_INV_W<CONF0_SPEC> {
333 IRDA_RX_INV_W::new(self, 13)
334 }
335 #[doc = "Bit 14 - Set this bit to enable uart loopback test mode."]
336 #[inline(always)]
337 pub fn loopback(&mut self) -> LOOPBACK_W<CONF0_SPEC> {
338 LOOPBACK_W::new(self, 14)
339 }
340 #[doc = "Bit 15 - Set this bit to enable transmitter's flow control function."]
341 #[inline(always)]
342 pub fn tx_flow_en(&mut self) -> TX_FLOW_EN_W<CONF0_SPEC> {
343 TX_FLOW_EN_W::new(self, 15)
344 }
345 #[doc = "Bit 16 - Set this bit to enable irda protocol."]
346 #[inline(always)]
347 pub fn irda_en(&mut self) -> IRDA_EN_W<CONF0_SPEC> {
348 IRDA_EN_W::new(self, 16)
349 }
350 #[doc = "Bit 17 - Set this bit to reset uart receiver's fifo."]
351 #[inline(always)]
352 pub fn rxfifo_rst(&mut self) -> RXFIFO_RST_W<CONF0_SPEC> {
353 RXFIFO_RST_W::new(self, 17)
354 }
355 #[doc = "Bit 18 - Set this bit to reset uart transmitter's fifo."]
356 #[inline(always)]
357 pub fn txfifo_rst(&mut self) -> TXFIFO_RST_W<CONF0_SPEC> {
358 TXFIFO_RST_W::new(self, 18)
359 }
360 #[doc = "Bit 19 - Set this bit to inverse the level value of uart rxd signal."]
361 #[inline(always)]
362 pub fn rxd_inv(&mut self) -> RXD_INV_W<CONF0_SPEC> {
363 RXD_INV_W::new(self, 19)
364 }
365 #[doc = "Bit 20 - Set this bit to inverse the level value of uart cts signal."]
366 #[inline(always)]
367 pub fn cts_inv(&mut self) -> CTS_INV_W<CONF0_SPEC> {
368 CTS_INV_W::new(self, 20)
369 }
370 #[doc = "Bit 21 - Set this bit to inverse the level value of uart dsr signal."]
371 #[inline(always)]
372 pub fn dsr_inv(&mut self) -> DSR_INV_W<CONF0_SPEC> {
373 DSR_INV_W::new(self, 21)
374 }
375 #[doc = "Bit 22 - Set this bit to inverse the level value of uart txd signal."]
376 #[inline(always)]
377 pub fn txd_inv(&mut self) -> TXD_INV_W<CONF0_SPEC> {
378 TXD_INV_W::new(self, 22)
379 }
380 #[doc = "Bit 23 - Set this bit to inverse the level value of uart rts signal."]
381 #[inline(always)]
382 pub fn rts_inv(&mut self) -> RTS_INV_W<CONF0_SPEC> {
383 RTS_INV_W::new(self, 23)
384 }
385 #[doc = "Bit 24 - Set this bit to inverse the level value of uart dtr signal."]
386 #[inline(always)]
387 pub fn dtr_inv(&mut self) -> DTR_INV_W<CONF0_SPEC> {
388 DTR_INV_W::new(self, 24)
389 }
390 #[doc = "Bit 25 - 1.force clock on for registers.support clock only when write registers"]
391 #[inline(always)]
392 pub fn clk_en(&mut self) -> CLK_EN_W<CONF0_SPEC> {
393 CLK_EN_W::new(self, 25)
394 }
395 #[doc = "Bit 26 - 1.receiver stops storing data int fifo when data is wrong. 0.receiver stores the data even if the received data is wrong."]
396 #[inline(always)]
397 pub fn err_wr_mask(&mut self) -> ERR_WR_MASK_W<CONF0_SPEC> {
398 ERR_WR_MASK_W::new(self, 26)
399 }
400 #[doc = "Bit 27 - This register is used to select the clock.1.apb clock 0:ref_tick"]
401 #[inline(always)]
402 pub fn tick_ref_always_on(&mut self) -> TICK_REF_ALWAYS_ON_W<CONF0_SPEC> {
403 TICK_REF_ALWAYS_ON_W::new(self, 27)
404 }
405}
406#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`conf0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`conf0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
407pub struct CONF0_SPEC;
408impl crate::RegisterSpec for CONF0_SPEC {
409 type Ux = u32;
410}
411#[doc = "`read()` method returns [`conf0::R`](R) reader structure"]
412impl crate::Readable for CONF0_SPEC {}
413#[doc = "`write(|w| ..)` method takes [`conf0::W`](W) writer structure"]
414impl crate::Writable for CONF0_SPEC {
415 type Safety = crate::Unsafe;
416}
417#[doc = "`reset()` method sets CONF0 to value 0x0800_001c"]
418impl crate::Resettable for CONF0_SPEC {
419 const RESET_VALUE: u32 = 0x0800_001c;
420}