esp32/rmt/
chstatus.rs

1#[doc = "Register `CH%sSTATUS` reader"]
2pub type R = crate::R<CHSTATUS_SPEC>;
3#[doc = "Field `STATUS` reader - The status for channel0"]
4pub type STATUS_R = crate::FieldReader<u32>;
5#[doc = "Field `MEM_WADDR_EX` reader - The current memory read address of channel0."]
6pub type MEM_WADDR_EX_R = crate::FieldReader<u16>;
7#[doc = "Field `MEM_RADDR_EX` reader - The current memory write address of channel0."]
8pub type MEM_RADDR_EX_R = crate::FieldReader<u16>;
9#[doc = "Field `STATE` reader - The channel0 state machine status register.3'h0 : idle, 3'h1 : send, 3'h2 : read memory, 3'h3 : receive, 3'h4 : wait."]
10pub type STATE_R = crate::FieldReader;
11#[doc = "Field `MEM_OWNER_ERR` reader - When channel0 is configured for receive mode, this bit will turn to high level if rmt_mem_owner register is not set to 1."]
12pub type MEM_OWNER_ERR_R = crate::BitReader;
13#[doc = "Field `MEM_FULL` reader - The memory full status bit for channel0 turns to high level when mem_waddr_ex is greater than or equal to the configuration range."]
14pub type MEM_FULL_R = crate::BitReader;
15#[doc = "Field `MEM_EMPTY` reader - The memory empty status bit for channel0. in acyclic mode, this bit turns to high level when mem_raddr_ex is greater than or equal to the configured range."]
16pub type MEM_EMPTY_R = crate::BitReader;
17#[doc = "Field `APB_MEM_WR_ERR` reader - The apb write memory status bit for channel0 turns to high level when the apb write address exceeds the configuration range."]
18pub type APB_MEM_WR_ERR_R = crate::BitReader;
19#[doc = "Field `APB_MEM_RD_ERR` reader - The apb read memory status bit for channel0 turns to high level when the apb read address exceeds the configuration range."]
20pub type APB_MEM_RD_ERR_R = crate::BitReader;
21impl R {
22    #[doc = "Bits 0:31 - The status for channel0"]
23    #[inline(always)]
24    pub fn status(&self) -> STATUS_R {
25        STATUS_R::new(self.bits)
26    }
27    #[doc = "Bits 0:9 - The current memory read address of channel0."]
28    #[inline(always)]
29    pub fn mem_waddr_ex(&self) -> MEM_WADDR_EX_R {
30        MEM_WADDR_EX_R::new((self.bits & 0x03ff) as u16)
31    }
32    #[doc = "Bits 12:21 - The current memory write address of channel0."]
33    #[inline(always)]
34    pub fn mem_raddr_ex(&self) -> MEM_RADDR_EX_R {
35        MEM_RADDR_EX_R::new(((self.bits >> 12) & 0x03ff) as u16)
36    }
37    #[doc = "Bits 24:26 - The channel0 state machine status register.3'h0 : idle, 3'h1 : send, 3'h2 : read memory, 3'h3 : receive, 3'h4 : wait."]
38    #[inline(always)]
39    pub fn state(&self) -> STATE_R {
40        STATE_R::new(((self.bits >> 24) & 7) as u8)
41    }
42    #[doc = "Bit 27 - When channel0 is configured for receive mode, this bit will turn to high level if rmt_mem_owner register is not set to 1."]
43    #[inline(always)]
44    pub fn mem_owner_err(&self) -> MEM_OWNER_ERR_R {
45        MEM_OWNER_ERR_R::new(((self.bits >> 27) & 1) != 0)
46    }
47    #[doc = "Bit 28 - The memory full status bit for channel0 turns to high level when mem_waddr_ex is greater than or equal to the configuration range."]
48    #[inline(always)]
49    pub fn mem_full(&self) -> MEM_FULL_R {
50        MEM_FULL_R::new(((self.bits >> 28) & 1) != 0)
51    }
52    #[doc = "Bit 29 - The memory empty status bit for channel0. in acyclic mode, this bit turns to high level when mem_raddr_ex is greater than or equal to the configured range."]
53    #[inline(always)]
54    pub fn mem_empty(&self) -> MEM_EMPTY_R {
55        MEM_EMPTY_R::new(((self.bits >> 29) & 1) != 0)
56    }
57    #[doc = "Bit 30 - The apb write memory status bit for channel0 turns to high level when the apb write address exceeds the configuration range."]
58    #[inline(always)]
59    pub fn apb_mem_wr_err(&self) -> APB_MEM_WR_ERR_R {
60        APB_MEM_WR_ERR_R::new(((self.bits >> 30) & 1) != 0)
61    }
62    #[doc = "Bit 31 - The apb read memory status bit for channel0 turns to high level when the apb read address exceeds the configuration range."]
63    #[inline(always)]
64    pub fn apb_mem_rd_err(&self) -> APB_MEM_RD_ERR_R {
65        APB_MEM_RD_ERR_R::new(((self.bits >> 31) & 1) != 0)
66    }
67}
68#[cfg(feature = "impl-register-debug")]
69impl core::fmt::Debug for R {
70    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
71        f.debug_struct("CHSTATUS")
72            .field("status", &self.status())
73            .field("mem_waddr_ex", &self.mem_waddr_ex())
74            .field("mem_raddr_ex", &self.mem_raddr_ex())
75            .field("state", &self.state())
76            .field("mem_owner_err", &self.mem_owner_err())
77            .field("mem_full", &self.mem_full())
78            .field("mem_empty", &self.mem_empty())
79            .field("apb_mem_wr_err", &self.apb_mem_wr_err())
80            .field("apb_mem_rd_err", &self.apb_mem_rd_err())
81            .finish()
82    }
83}
84#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`chstatus::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
85pub struct CHSTATUS_SPEC;
86impl crate::RegisterSpec for CHSTATUS_SPEC {
87    type Ux = u32;
88}
89#[doc = "`read()` method returns [`chstatus::R`](R) reader structure"]
90impl crate::Readable for CHSTATUS_SPEC {}
91#[doc = "`reset()` method sets CH%sSTATUS to value 0"]
92impl crate::Resettable for CHSTATUS_SPEC {}
esp32/rmt/chstatus.rs

esp32/rmt/
chstatus.rs
