1#[doc = "Register `INT_ENA` reader"]
2pub type R = crate::R<INT_ENA_SPEC>;
3#[doc = "Register `INT_ENA` writer"]
4pub type W = crate::W<INT_ENA_SPEC>;
5#[doc = "Field `HSTIMER_OVF(0-3)` reader - The interrupt enable bit for high speed channel%s counter overflow interrupt."]
6pub type HSTIMER_OVF_R = crate::BitReader;
7#[doc = "Field `HSTIMER_OVF(0-3)` writer - The interrupt enable bit for high speed channel%s counter overflow interrupt."]
8pub type HSTIMER_OVF_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `LSTIMER_OVF(0-3)` reader - The interrupt enable bit for low speed channel%s counter overflow interrupt."]
10pub type LSTIMER_OVF_R = crate::BitReader;
11#[doc = "Field `LSTIMER_OVF(0-3)` writer - The interrupt enable bit for low speed channel%s counter overflow interrupt."]
12pub type LSTIMER_OVF_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `DUTY_CHNG_END_HSCH(0-7)` reader - The interrupt enable bit for high speed channel %s duty change done interrupt."]
14pub type DUTY_CHNG_END_HSCH_R = crate::BitReader;
15#[doc = "Field `DUTY_CHNG_END_HSCH(0-7)` writer - The interrupt enable bit for high speed channel %s duty change done interrupt."]
16pub type DUTY_CHNG_END_HSCH_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `DUTY_CHNG_END_LSCH(0-7)` reader - The interrupt enable bit for low speed channel %s duty change done interrupt."]
18pub type DUTY_CHNG_END_LSCH_R = crate::BitReader;
19#[doc = "Field `DUTY_CHNG_END_LSCH(0-7)` writer - The interrupt enable bit for low speed channel %s duty change done interrupt."]
20pub type DUTY_CHNG_END_LSCH_W<'a, REG> = crate::BitWriter<'a, REG>;
21impl R {
22 #[doc = "The interrupt enable bit for high speed channel(0-3) counter overflow interrupt."]
23 #[doc = ""]
24 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `HSTIMER0_OVF` field.</div>"]
25 #[inline(always)]
26 pub fn hstimer_ovf(&self, n: u8) -> HSTIMER_OVF_R {
27 #[allow(clippy::no_effect)]
28 [(); 4][n as usize];
29 HSTIMER_OVF_R::new(((self.bits >> n) & 1) != 0)
30 }
31 #[doc = "Iterator for array of:"]
32 #[doc = "The interrupt enable bit for high speed channel(0-3) counter overflow interrupt."]
33 #[inline(always)]
34 pub fn hstimer_ovf_iter(&self) -> impl Iterator<Item = HSTIMER_OVF_R> + '_ {
35 (0..4).map(move |n| HSTIMER_OVF_R::new(((self.bits >> n) & 1) != 0))
36 }
37 #[doc = "Bit 0 - The interrupt enable bit for high speed channel0 counter overflow interrupt."]
38 #[inline(always)]
39 pub fn hstimer0_ovf(&self) -> HSTIMER_OVF_R {
40 HSTIMER_OVF_R::new((self.bits & 1) != 0)
41 }
42 #[doc = "Bit 1 - The interrupt enable bit for high speed channel1 counter overflow interrupt."]
43 #[inline(always)]
44 pub fn hstimer1_ovf(&self) -> HSTIMER_OVF_R {
45 HSTIMER_OVF_R::new(((self.bits >> 1) & 1) != 0)
46 }
47 #[doc = "Bit 2 - The interrupt enable bit for high speed channel2 counter overflow interrupt."]
48 #[inline(always)]
49 pub fn hstimer2_ovf(&self) -> HSTIMER_OVF_R {
50 HSTIMER_OVF_R::new(((self.bits >> 2) & 1) != 0)
51 }
52 #[doc = "Bit 3 - The interrupt enable bit for high speed channel3 counter overflow interrupt."]
53 #[inline(always)]
54 pub fn hstimer3_ovf(&self) -> HSTIMER_OVF_R {
55 HSTIMER_OVF_R::new(((self.bits >> 3) & 1) != 0)
56 }
57 #[doc = "The interrupt enable bit for low speed channel(0-3) counter overflow interrupt."]
58 #[doc = ""]
59 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `LSTIMER0_OVF` field.</div>"]
60 #[inline(always)]
61 pub fn lstimer_ovf(&self, n: u8) -> LSTIMER_OVF_R {
62 #[allow(clippy::no_effect)]
63 [(); 4][n as usize];
64 LSTIMER_OVF_R::new(((self.bits >> (n + 4)) & 1) != 0)
65 }
66 #[doc = "Iterator for array of:"]
67 #[doc = "The interrupt enable bit for low speed channel(0-3) counter overflow interrupt."]
68 #[inline(always)]
69 pub fn lstimer_ovf_iter(&self) -> impl Iterator<Item = LSTIMER_OVF_R> + '_ {
70 (0..4).map(move |n| LSTIMER_OVF_R::new(((self.bits >> (n + 4)) & 1) != 0))
71 }
72 #[doc = "Bit 4 - The interrupt enable bit for low speed channel0 counter overflow interrupt."]
73 #[inline(always)]
74 pub fn lstimer0_ovf(&self) -> LSTIMER_OVF_R {
75 LSTIMER_OVF_R::new(((self.bits >> 4) & 1) != 0)
76 }
77 #[doc = "Bit 5 - The interrupt enable bit for low speed channel1 counter overflow interrupt."]
78 #[inline(always)]
79 pub fn lstimer1_ovf(&self) -> LSTIMER_OVF_R {
80 LSTIMER_OVF_R::new(((self.bits >> 5) & 1) != 0)
81 }
82 #[doc = "Bit 6 - The interrupt enable bit for low speed channel2 counter overflow interrupt."]
83 #[inline(always)]
84 pub fn lstimer2_ovf(&self) -> LSTIMER_OVF_R {
85 LSTIMER_OVF_R::new(((self.bits >> 6) & 1) != 0)
86 }
87 #[doc = "Bit 7 - The interrupt enable bit for low speed channel3 counter overflow interrupt."]
88 #[inline(always)]
89 pub fn lstimer3_ovf(&self) -> LSTIMER_OVF_R {
90 LSTIMER_OVF_R::new(((self.bits >> 7) & 1) != 0)
91 }
92 #[doc = "The interrupt enable bit for high speed channel (0-7) duty change done interrupt."]
93 #[doc = ""]
94 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `DUTY_CHNG_END_HSCH0` field.</div>"]
95 #[inline(always)]
96 pub fn duty_chng_end_hsch(&self, n: u8) -> DUTY_CHNG_END_HSCH_R {
97 #[allow(clippy::no_effect)]
98 [(); 8][n as usize];
99 DUTY_CHNG_END_HSCH_R::new(((self.bits >> (n + 8)) & 1) != 0)
100 }
101 #[doc = "Iterator for array of:"]
102 #[doc = "The interrupt enable bit for high speed channel (0-7) duty change done interrupt."]
103 #[inline(always)]
104 pub fn duty_chng_end_hsch_iter(&self) -> impl Iterator<Item = DUTY_CHNG_END_HSCH_R> + '_ {
105 (0..8).map(move |n| DUTY_CHNG_END_HSCH_R::new(((self.bits >> (n + 8)) & 1) != 0))
106 }
107 #[doc = "Bit 8 - The interrupt enable bit for high speed channel 0 duty change done interrupt."]
108 #[inline(always)]
109 pub fn duty_chng_end_hsch0(&self) -> DUTY_CHNG_END_HSCH_R {
110 DUTY_CHNG_END_HSCH_R::new(((self.bits >> 8) & 1) != 0)
111 }
112 #[doc = "Bit 9 - The interrupt enable bit for high speed channel 1 duty change done interrupt."]
113 #[inline(always)]
114 pub fn duty_chng_end_hsch1(&self) -> DUTY_CHNG_END_HSCH_R {
115 DUTY_CHNG_END_HSCH_R::new(((self.bits >> 9) & 1) != 0)
116 }
117 #[doc = "Bit 10 - The interrupt enable bit for high speed channel 2 duty change done interrupt."]
118 #[inline(always)]
119 pub fn duty_chng_end_hsch2(&self) -> DUTY_CHNG_END_HSCH_R {
120 DUTY_CHNG_END_HSCH_R::new(((self.bits >> 10) & 1) != 0)
121 }
122 #[doc = "Bit 11 - The interrupt enable bit for high speed channel 3 duty change done interrupt."]
123 #[inline(always)]
124 pub fn duty_chng_end_hsch3(&self) -> DUTY_CHNG_END_HSCH_R {
125 DUTY_CHNG_END_HSCH_R::new(((self.bits >> 11) & 1) != 0)
126 }
127 #[doc = "Bit 12 - The interrupt enable bit for high speed channel 4 duty change done interrupt."]
128 #[inline(always)]
129 pub fn duty_chng_end_hsch4(&self) -> DUTY_CHNG_END_HSCH_R {
130 DUTY_CHNG_END_HSCH_R::new(((self.bits >> 12) & 1) != 0)
131 }
132 #[doc = "Bit 13 - The interrupt enable bit for high speed channel 5 duty change done interrupt."]
133 #[inline(always)]
134 pub fn duty_chng_end_hsch5(&self) -> DUTY_CHNG_END_HSCH_R {
135 DUTY_CHNG_END_HSCH_R::new(((self.bits >> 13) & 1) != 0)
136 }
137 #[doc = "Bit 14 - The interrupt enable bit for high speed channel 6 duty change done interrupt."]
138 #[inline(always)]
139 pub fn duty_chng_end_hsch6(&self) -> DUTY_CHNG_END_HSCH_R {
140 DUTY_CHNG_END_HSCH_R::new(((self.bits >> 14) & 1) != 0)
141 }
142 #[doc = "Bit 15 - The interrupt enable bit for high speed channel 7 duty change done interrupt."]
143 #[inline(always)]
144 pub fn duty_chng_end_hsch7(&self) -> DUTY_CHNG_END_HSCH_R {
145 DUTY_CHNG_END_HSCH_R::new(((self.bits >> 15) & 1) != 0)
146 }
147 #[doc = "The interrupt enable bit for low speed channel (0-7) duty change done interrupt."]
148 #[doc = ""]
149 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `DUTY_CHNG_END_LSCH0` field.</div>"]
150 #[inline(always)]
151 pub fn duty_chng_end_lsch(&self, n: u8) -> DUTY_CHNG_END_LSCH_R {
152 #[allow(clippy::no_effect)]
153 [(); 8][n as usize];
154 DUTY_CHNG_END_LSCH_R::new(((self.bits >> (n + 16)) & 1) != 0)
155 }
156 #[doc = "Iterator for array of:"]
157 #[doc = "The interrupt enable bit for low speed channel (0-7) duty change done interrupt."]
158 #[inline(always)]
159 pub fn duty_chng_end_lsch_iter(&self) -> impl Iterator<Item = DUTY_CHNG_END_LSCH_R> + '_ {
160 (0..8).map(move |n| DUTY_CHNG_END_LSCH_R::new(((self.bits >> (n + 16)) & 1) != 0))
161 }
162 #[doc = "Bit 16 - The interrupt enable bit for low speed channel 0 duty change done interrupt."]
163 #[inline(always)]
164 pub fn duty_chng_end_lsch0(&self) -> DUTY_CHNG_END_LSCH_R {
165 DUTY_CHNG_END_LSCH_R::new(((self.bits >> 16) & 1) != 0)
166 }
167 #[doc = "Bit 17 - The interrupt enable bit for low speed channel 1 duty change done interrupt."]
168 #[inline(always)]
169 pub fn duty_chng_end_lsch1(&self) -> DUTY_CHNG_END_LSCH_R {
170 DUTY_CHNG_END_LSCH_R::new(((self.bits >> 17) & 1) != 0)
171 }
172 #[doc = "Bit 18 - The interrupt enable bit for low speed channel 2 duty change done interrupt."]
173 #[inline(always)]
174 pub fn duty_chng_end_lsch2(&self) -> DUTY_CHNG_END_LSCH_R {
175 DUTY_CHNG_END_LSCH_R::new(((self.bits >> 18) & 1) != 0)
176 }
177 #[doc = "Bit 19 - The interrupt enable bit for low speed channel 3 duty change done interrupt."]
178 #[inline(always)]
179 pub fn duty_chng_end_lsch3(&self) -> DUTY_CHNG_END_LSCH_R {
180 DUTY_CHNG_END_LSCH_R::new(((self.bits >> 19) & 1) != 0)
181 }
182 #[doc = "Bit 20 - The interrupt enable bit for low speed channel 4 duty change done interrupt."]
183 #[inline(always)]
184 pub fn duty_chng_end_lsch4(&self) -> DUTY_CHNG_END_LSCH_R {
185 DUTY_CHNG_END_LSCH_R::new(((self.bits >> 20) & 1) != 0)
186 }
187 #[doc = "Bit 21 - The interrupt enable bit for low speed channel 5 duty change done interrupt."]
188 #[inline(always)]
189 pub fn duty_chng_end_lsch5(&self) -> DUTY_CHNG_END_LSCH_R {
190 DUTY_CHNG_END_LSCH_R::new(((self.bits >> 21) & 1) != 0)
191 }
192 #[doc = "Bit 22 - The interrupt enable bit for low speed channel 6 duty change done interrupt."]
193 #[inline(always)]
194 pub fn duty_chng_end_lsch6(&self) -> DUTY_CHNG_END_LSCH_R {
195 DUTY_CHNG_END_LSCH_R::new(((self.bits >> 22) & 1) != 0)
196 }
197 #[doc = "Bit 23 - The interrupt enable bit for low speed channel 7 duty change done interrupt."]
198 #[inline(always)]
199 pub fn duty_chng_end_lsch7(&self) -> DUTY_CHNG_END_LSCH_R {
200 DUTY_CHNG_END_LSCH_R::new(((self.bits >> 23) & 1) != 0)
201 }
202}
203#[cfg(feature = "impl-register-debug")]
204impl core::fmt::Debug for R {
205 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
206 f.debug_struct("INT_ENA")
207 .field("hstimer0_ovf", &self.hstimer0_ovf())
208 .field("hstimer1_ovf", &self.hstimer1_ovf())
209 .field("hstimer2_ovf", &self.hstimer2_ovf())
210 .field("hstimer3_ovf", &self.hstimer3_ovf())
211 .field("lstimer0_ovf", &self.lstimer0_ovf())
212 .field("lstimer1_ovf", &self.lstimer1_ovf())
213 .field("lstimer2_ovf", &self.lstimer2_ovf())
214 .field("lstimer3_ovf", &self.lstimer3_ovf())
215 .field("duty_chng_end_hsch0", &self.duty_chng_end_hsch0())
216 .field("duty_chng_end_hsch1", &self.duty_chng_end_hsch1())
217 .field("duty_chng_end_hsch2", &self.duty_chng_end_hsch2())
218 .field("duty_chng_end_hsch3", &self.duty_chng_end_hsch3())
219 .field("duty_chng_end_hsch4", &self.duty_chng_end_hsch4())
220 .field("duty_chng_end_hsch5", &self.duty_chng_end_hsch5())
221 .field("duty_chng_end_hsch6", &self.duty_chng_end_hsch6())
222 .field("duty_chng_end_hsch7", &self.duty_chng_end_hsch7())
223 .field("duty_chng_end_lsch0", &self.duty_chng_end_lsch0())
224 .field("duty_chng_end_lsch1", &self.duty_chng_end_lsch1())
225 .field("duty_chng_end_lsch2", &self.duty_chng_end_lsch2())
226 .field("duty_chng_end_lsch3", &self.duty_chng_end_lsch3())
227 .field("duty_chng_end_lsch4", &self.duty_chng_end_lsch4())
228 .field("duty_chng_end_lsch5", &self.duty_chng_end_lsch5())
229 .field("duty_chng_end_lsch6", &self.duty_chng_end_lsch6())
230 .field("duty_chng_end_lsch7", &self.duty_chng_end_lsch7())
231 .finish()
232 }
233}
234impl W {
235 #[doc = "The interrupt enable bit for high speed channel(0-3) counter overflow interrupt."]
236 #[doc = ""]
237 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `HSTIMER0_OVF` field.</div>"]
238 #[inline(always)]
239 pub fn hstimer_ovf(&mut self, n: u8) -> HSTIMER_OVF_W<INT_ENA_SPEC> {
240 #[allow(clippy::no_effect)]
241 [(); 4][n as usize];
242 HSTIMER_OVF_W::new(self, n)
243 }
244 #[doc = "Bit 0 - The interrupt enable bit for high speed channel0 counter overflow interrupt."]
245 #[inline(always)]
246 pub fn hstimer0_ovf(&mut self) -> HSTIMER_OVF_W<INT_ENA_SPEC> {
247 HSTIMER_OVF_W::new(self, 0)
248 }
249 #[doc = "Bit 1 - The interrupt enable bit for high speed channel1 counter overflow interrupt."]
250 #[inline(always)]
251 pub fn hstimer1_ovf(&mut self) -> HSTIMER_OVF_W<INT_ENA_SPEC> {
252 HSTIMER_OVF_W::new(self, 1)
253 }
254 #[doc = "Bit 2 - The interrupt enable bit for high speed channel2 counter overflow interrupt."]
255 #[inline(always)]
256 pub fn hstimer2_ovf(&mut self) -> HSTIMER_OVF_W<INT_ENA_SPEC> {
257 HSTIMER_OVF_W::new(self, 2)
258 }
259 #[doc = "Bit 3 - The interrupt enable bit for high speed channel3 counter overflow interrupt."]
260 #[inline(always)]
261 pub fn hstimer3_ovf(&mut self) -> HSTIMER_OVF_W<INT_ENA_SPEC> {
262 HSTIMER_OVF_W::new(self, 3)
263 }
264 #[doc = "The interrupt enable bit for low speed channel(0-3) counter overflow interrupt."]
265 #[doc = ""]
266 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `LSTIMER0_OVF` field.</div>"]
267 #[inline(always)]
268 pub fn lstimer_ovf(&mut self, n: u8) -> LSTIMER_OVF_W<INT_ENA_SPEC> {
269 #[allow(clippy::no_effect)]
270 [(); 4][n as usize];
271 LSTIMER_OVF_W::new(self, n + 4)
272 }
273 #[doc = "Bit 4 - The interrupt enable bit for low speed channel0 counter overflow interrupt."]
274 #[inline(always)]
275 pub fn lstimer0_ovf(&mut self) -> LSTIMER_OVF_W<INT_ENA_SPEC> {
276 LSTIMER_OVF_W::new(self, 4)
277 }
278 #[doc = "Bit 5 - The interrupt enable bit for low speed channel1 counter overflow interrupt."]
279 #[inline(always)]
280 pub fn lstimer1_ovf(&mut self) -> LSTIMER_OVF_W<INT_ENA_SPEC> {
281 LSTIMER_OVF_W::new(self, 5)
282 }
283 #[doc = "Bit 6 - The interrupt enable bit for low speed channel2 counter overflow interrupt."]
284 #[inline(always)]
285 pub fn lstimer2_ovf(&mut self) -> LSTIMER_OVF_W<INT_ENA_SPEC> {
286 LSTIMER_OVF_W::new(self, 6)
287 }
288 #[doc = "Bit 7 - The interrupt enable bit for low speed channel3 counter overflow interrupt."]
289 #[inline(always)]
290 pub fn lstimer3_ovf(&mut self) -> LSTIMER_OVF_W<INT_ENA_SPEC> {
291 LSTIMER_OVF_W::new(self, 7)
292 }
293 #[doc = "The interrupt enable bit for high speed channel (0-7) duty change done interrupt."]
294 #[doc = ""]
295 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `DUTY_CHNG_END_HSCH0` field.</div>"]
296 #[inline(always)]
297 pub fn duty_chng_end_hsch(&mut self, n: u8) -> DUTY_CHNG_END_HSCH_W<INT_ENA_SPEC> {
298 #[allow(clippy::no_effect)]
299 [(); 8][n as usize];
300 DUTY_CHNG_END_HSCH_W::new(self, n + 8)
301 }
302 #[doc = "Bit 8 - The interrupt enable bit for high speed channel 0 duty change done interrupt."]
303 #[inline(always)]
304 pub fn duty_chng_end_hsch0(&mut self) -> DUTY_CHNG_END_HSCH_W<INT_ENA_SPEC> {
305 DUTY_CHNG_END_HSCH_W::new(self, 8)
306 }
307 #[doc = "Bit 9 - The interrupt enable bit for high speed channel 1 duty change done interrupt."]
308 #[inline(always)]
309 pub fn duty_chng_end_hsch1(&mut self) -> DUTY_CHNG_END_HSCH_W<INT_ENA_SPEC> {
310 DUTY_CHNG_END_HSCH_W::new(self, 9)
311 }
312 #[doc = "Bit 10 - The interrupt enable bit for high speed channel 2 duty change done interrupt."]
313 #[inline(always)]
314 pub fn duty_chng_end_hsch2(&mut self) -> DUTY_CHNG_END_HSCH_W<INT_ENA_SPEC> {
315 DUTY_CHNG_END_HSCH_W::new(self, 10)
316 }
317 #[doc = "Bit 11 - The interrupt enable bit for high speed channel 3 duty change done interrupt."]
318 #[inline(always)]
319 pub fn duty_chng_end_hsch3(&mut self) -> DUTY_CHNG_END_HSCH_W<INT_ENA_SPEC> {
320 DUTY_CHNG_END_HSCH_W::new(self, 11)
321 }
322 #[doc = "Bit 12 - The interrupt enable bit for high speed channel 4 duty change done interrupt."]
323 #[inline(always)]
324 pub fn duty_chng_end_hsch4(&mut self) -> DUTY_CHNG_END_HSCH_W<INT_ENA_SPEC> {
325 DUTY_CHNG_END_HSCH_W::new(self, 12)
326 }
327 #[doc = "Bit 13 - The interrupt enable bit for high speed channel 5 duty change done interrupt."]
328 #[inline(always)]
329 pub fn duty_chng_end_hsch5(&mut self) -> DUTY_CHNG_END_HSCH_W<INT_ENA_SPEC> {
330 DUTY_CHNG_END_HSCH_W::new(self, 13)
331 }
332 #[doc = "Bit 14 - The interrupt enable bit for high speed channel 6 duty change done interrupt."]
333 #[inline(always)]
334 pub fn duty_chng_end_hsch6(&mut self) -> DUTY_CHNG_END_HSCH_W<INT_ENA_SPEC> {
335 DUTY_CHNG_END_HSCH_W::new(self, 14)
336 }
337 #[doc = "Bit 15 - The interrupt enable bit for high speed channel 7 duty change done interrupt."]
338 #[inline(always)]
339 pub fn duty_chng_end_hsch7(&mut self) -> DUTY_CHNG_END_HSCH_W<INT_ENA_SPEC> {
340 DUTY_CHNG_END_HSCH_W::new(self, 15)
341 }
342 #[doc = "The interrupt enable bit for low speed channel (0-7) duty change done interrupt."]
343 #[doc = ""]
344 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `DUTY_CHNG_END_LSCH0` field.</div>"]
345 #[inline(always)]
346 pub fn duty_chng_end_lsch(&mut self, n: u8) -> DUTY_CHNG_END_LSCH_W<INT_ENA_SPEC> {
347 #[allow(clippy::no_effect)]
348 [(); 8][n as usize];
349 DUTY_CHNG_END_LSCH_W::new(self, n + 16)
350 }
351 #[doc = "Bit 16 - The interrupt enable bit for low speed channel 0 duty change done interrupt."]
352 #[inline(always)]
353 pub fn duty_chng_end_lsch0(&mut self) -> DUTY_CHNG_END_LSCH_W<INT_ENA_SPEC> {
354 DUTY_CHNG_END_LSCH_W::new(self, 16)
355 }
356 #[doc = "Bit 17 - The interrupt enable bit for low speed channel 1 duty change done interrupt."]
357 #[inline(always)]
358 pub fn duty_chng_end_lsch1(&mut self) -> DUTY_CHNG_END_LSCH_W<INT_ENA_SPEC> {
359 DUTY_CHNG_END_LSCH_W::new(self, 17)
360 }
361 #[doc = "Bit 18 - The interrupt enable bit for low speed channel 2 duty change done interrupt."]
362 #[inline(always)]
363 pub fn duty_chng_end_lsch2(&mut self) -> DUTY_CHNG_END_LSCH_W<INT_ENA_SPEC> {
364 DUTY_CHNG_END_LSCH_W::new(self, 18)
365 }
366 #[doc = "Bit 19 - The interrupt enable bit for low speed channel 3 duty change done interrupt."]
367 #[inline(always)]
368 pub fn duty_chng_end_lsch3(&mut self) -> DUTY_CHNG_END_LSCH_W<INT_ENA_SPEC> {
369 DUTY_CHNG_END_LSCH_W::new(self, 19)
370 }
371 #[doc = "Bit 20 - The interrupt enable bit for low speed channel 4 duty change done interrupt."]
372 #[inline(always)]
373 pub fn duty_chng_end_lsch4(&mut self) -> DUTY_CHNG_END_LSCH_W<INT_ENA_SPEC> {
374 DUTY_CHNG_END_LSCH_W::new(self, 20)
375 }
376 #[doc = "Bit 21 - The interrupt enable bit for low speed channel 5 duty change done interrupt."]
377 #[inline(always)]
378 pub fn duty_chng_end_lsch5(&mut self) -> DUTY_CHNG_END_LSCH_W<INT_ENA_SPEC> {
379 DUTY_CHNG_END_LSCH_W::new(self, 21)
380 }
381 #[doc = "Bit 22 - The interrupt enable bit for low speed channel 6 duty change done interrupt."]
382 #[inline(always)]
383 pub fn duty_chng_end_lsch6(&mut self) -> DUTY_CHNG_END_LSCH_W<INT_ENA_SPEC> {
384 DUTY_CHNG_END_LSCH_W::new(self, 22)
385 }
386 #[doc = "Bit 23 - The interrupt enable bit for low speed channel 7 duty change done interrupt."]
387 #[inline(always)]
388 pub fn duty_chng_end_lsch7(&mut self) -> DUTY_CHNG_END_LSCH_W<INT_ENA_SPEC> {
389 DUTY_CHNG_END_LSCH_W::new(self, 23)
390 }
391}
392#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
393pub struct INT_ENA_SPEC;
394impl crate::RegisterSpec for INT_ENA_SPEC {
395 type Ux = u32;
396}
397#[doc = "`read()` method returns [`int_ena::R`](R) reader structure"]
398impl crate::Readable for INT_ENA_SPEC {}
399#[doc = "`write(|w| ..)` method takes [`int_ena::W`](W) writer structure"]
400impl crate::Writable for INT_ENA_SPEC {
401 type Safety = crate::Unsafe;
402}
403#[doc = "`reset()` method sets INT_ENA to value 0"]
404impl crate::Resettable for INT_ENA_SPEC {}