1#[doc = "Register `CTR` reader"]
2pub type R = crate::R<CTR_SPEC>;
3#[doc = "Register `CTR` writer"]
4pub type W = crate::W<CTR_SPEC>;
5#[doc = "Field `SDA_FORCE_OUT` reader - 1: normally ouput sda data 0: exchange the function of sda_o and sda_oe (sda_o is the original internal output sda signal sda_oe is the enable bit for the internal output sda signal)"]
6pub type SDA_FORCE_OUT_R = crate::BitReader;
7#[doc = "Field `SDA_FORCE_OUT` writer - 1: normally ouput sda data 0: exchange the function of sda_o and sda_oe (sda_o is the original internal output sda signal sda_oe is the enable bit for the internal output sda signal)"]
8pub type SDA_FORCE_OUT_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `SCL_FORCE_OUT` reader - 1: normally ouput scl clock 0: exchange the function of scl_o and scl_oe (scl_o is the original internal output scl signal scl_oe is the enable bit for the internal output scl signal)"]
10pub type SCL_FORCE_OUT_R = crate::BitReader;
11#[doc = "Field `SCL_FORCE_OUT` writer - 1: normally ouput scl clock 0: exchange the function of scl_o and scl_oe (scl_o is the original internal output scl signal scl_oe is the enable bit for the internal output scl signal)"]
12pub type SCL_FORCE_OUT_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `SAMPLE_SCL_LEVEL` reader - Set this bit to sample data in SCL low level. clear this bit to sample data in SCL high level."]
14pub type SAMPLE_SCL_LEVEL_R = crate::BitReader;
15#[doc = "Field `SAMPLE_SCL_LEVEL` writer - Set this bit to sample data in SCL low level. clear this bit to sample data in SCL high level."]
16pub type SAMPLE_SCL_LEVEL_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `MS_MODE` reader - Set this bit to configure the module as i2c master clear this bit to configure the module as i2c slave."]
18pub type MS_MODE_R = crate::BitReader;
19#[doc = "Field `MS_MODE` writer - Set this bit to configure the module as i2c master clear this bit to configure the module as i2c slave."]
20pub type MS_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `TRANS_START` reader - Set this bit to start sending data in txfifo."]
22pub type TRANS_START_R = crate::BitReader;
23#[doc = "Field `TRANS_START` writer - Set this bit to start sending data in txfifo."]
24pub type TRANS_START_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `TX_LSB_FIRST` reader - This bit is used to control the sending mode for data need to be send. 1: receive data from most significant bit 0: receive data from least significant bit"]
26pub type TX_LSB_FIRST_R = crate::BitReader;
27#[doc = "Field `TX_LSB_FIRST` writer - This bit is used to control the sending mode for data need to be send. 1: receive data from most significant bit 0: receive data from least significant bit"]
28pub type TX_LSB_FIRST_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `RX_LSB_FIRST` reader - This bit is used to control the storage mode for received datas. 1: receive data from most significant bit 0: receive data from least significant bit"]
30pub type RX_LSB_FIRST_R = crate::BitReader;
31#[doc = "Field `RX_LSB_FIRST` writer - This bit is used to control the storage mode for received datas. 1: receive data from most significant bit 0: receive data from least significant bit"]
32pub type RX_LSB_FIRST_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `CLK_EN` reader - This is the clock gating control bit for reading or writing registers."]
34pub type CLK_EN_R = crate::BitReader;
35#[doc = "Field `CLK_EN` writer - This is the clock gating control bit for reading or writing registers."]
36pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
37impl R {
38 #[doc = "Bit 0 - 1: normally ouput sda data 0: exchange the function of sda_o and sda_oe (sda_o is the original internal output sda signal sda_oe is the enable bit for the internal output sda signal)"]
39 #[inline(always)]
40 pub fn sda_force_out(&self) -> SDA_FORCE_OUT_R {
41 SDA_FORCE_OUT_R::new((self.bits & 1) != 0)
42 }
43 #[doc = "Bit 1 - 1: normally ouput scl clock 0: exchange the function of scl_o and scl_oe (scl_o is the original internal output scl signal scl_oe is the enable bit for the internal output scl signal)"]
44 #[inline(always)]
45 pub fn scl_force_out(&self) -> SCL_FORCE_OUT_R {
46 SCL_FORCE_OUT_R::new(((self.bits >> 1) & 1) != 0)
47 }
48 #[doc = "Bit 2 - Set this bit to sample data in SCL low level. clear this bit to sample data in SCL high level."]
49 #[inline(always)]
50 pub fn sample_scl_level(&self) -> SAMPLE_SCL_LEVEL_R {
51 SAMPLE_SCL_LEVEL_R::new(((self.bits >> 2) & 1) != 0)
52 }
53 #[doc = "Bit 4 - Set this bit to configure the module as i2c master clear this bit to configure the module as i2c slave."]
54 #[inline(always)]
55 pub fn ms_mode(&self) -> MS_MODE_R {
56 MS_MODE_R::new(((self.bits >> 4) & 1) != 0)
57 }
58 #[doc = "Bit 5 - Set this bit to start sending data in txfifo."]
59 #[inline(always)]
60 pub fn trans_start(&self) -> TRANS_START_R {
61 TRANS_START_R::new(((self.bits >> 5) & 1) != 0)
62 }
63 #[doc = "Bit 6 - This bit is used to control the sending mode for data need to be send. 1: receive data from most significant bit 0: receive data from least significant bit"]
64 #[inline(always)]
65 pub fn tx_lsb_first(&self) -> TX_LSB_FIRST_R {
66 TX_LSB_FIRST_R::new(((self.bits >> 6) & 1) != 0)
67 }
68 #[doc = "Bit 7 - This bit is used to control the storage mode for received datas. 1: receive data from most significant bit 0: receive data from least significant bit"]
69 #[inline(always)]
70 pub fn rx_lsb_first(&self) -> RX_LSB_FIRST_R {
71 RX_LSB_FIRST_R::new(((self.bits >> 7) & 1) != 0)
72 }
73 #[doc = "Bit 8 - This is the clock gating control bit for reading or writing registers."]
74 #[inline(always)]
75 pub fn clk_en(&self) -> CLK_EN_R {
76 CLK_EN_R::new(((self.bits >> 8) & 1) != 0)
77 }
78}
79#[cfg(feature = "impl-register-debug")]
80impl core::fmt::Debug for R {
81 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
82 f.debug_struct("CTR")
83 .field("sda_force_out", &self.sda_force_out())
84 .field("scl_force_out", &self.scl_force_out())
85 .field("sample_scl_level", &self.sample_scl_level())
86 .field("ms_mode", &self.ms_mode())
87 .field("trans_start", &self.trans_start())
88 .field("tx_lsb_first", &self.tx_lsb_first())
89 .field("rx_lsb_first", &self.rx_lsb_first())
90 .field("clk_en", &self.clk_en())
91 .finish()
92 }
93}
94impl W {
95 #[doc = "Bit 0 - 1: normally ouput sda data 0: exchange the function of sda_o and sda_oe (sda_o is the original internal output sda signal sda_oe is the enable bit for the internal output sda signal)"]
96 #[inline(always)]
97 pub fn sda_force_out(&mut self) -> SDA_FORCE_OUT_W<CTR_SPEC> {
98 SDA_FORCE_OUT_W::new(self, 0)
99 }
100 #[doc = "Bit 1 - 1: normally ouput scl clock 0: exchange the function of scl_o and scl_oe (scl_o is the original internal output scl signal scl_oe is the enable bit for the internal output scl signal)"]
101 #[inline(always)]
102 pub fn scl_force_out(&mut self) -> SCL_FORCE_OUT_W<CTR_SPEC> {
103 SCL_FORCE_OUT_W::new(self, 1)
104 }
105 #[doc = "Bit 2 - Set this bit to sample data in SCL low level. clear this bit to sample data in SCL high level."]
106 #[inline(always)]
107 pub fn sample_scl_level(&mut self) -> SAMPLE_SCL_LEVEL_W<CTR_SPEC> {
108 SAMPLE_SCL_LEVEL_W::new(self, 2)
109 }
110 #[doc = "Bit 4 - Set this bit to configure the module as i2c master clear this bit to configure the module as i2c slave."]
111 #[inline(always)]
112 pub fn ms_mode(&mut self) -> MS_MODE_W<CTR_SPEC> {
113 MS_MODE_W::new(self, 4)
114 }
115 #[doc = "Bit 5 - Set this bit to start sending data in txfifo."]
116 #[inline(always)]
117 pub fn trans_start(&mut self) -> TRANS_START_W<CTR_SPEC> {
118 TRANS_START_W::new(self, 5)
119 }
120 #[doc = "Bit 6 - This bit is used to control the sending mode for data need to be send. 1: receive data from most significant bit 0: receive data from least significant bit"]
121 #[inline(always)]
122 pub fn tx_lsb_first(&mut self) -> TX_LSB_FIRST_W<CTR_SPEC> {
123 TX_LSB_FIRST_W::new(self, 6)
124 }
125 #[doc = "Bit 7 - This bit is used to control the storage mode for received datas. 1: receive data from most significant bit 0: receive data from least significant bit"]
126 #[inline(always)]
127 pub fn rx_lsb_first(&mut self) -> RX_LSB_FIRST_W<CTR_SPEC> {
128 RX_LSB_FIRST_W::new(self, 7)
129 }
130 #[doc = "Bit 8 - This is the clock gating control bit for reading or writing registers."]
131 #[inline(always)]
132 pub fn clk_en(&mut self) -> CLK_EN_W<CTR_SPEC> {
133 CLK_EN_W::new(self, 8)
134 }
135}
136#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`ctr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
137pub struct CTR_SPEC;
138impl crate::RegisterSpec for CTR_SPEC {
139 type Ux = u32;
140}
141#[doc = "`read()` method returns [`ctr::R`](R) reader structure"]
142impl crate::Readable for CTR_SPEC {}
143#[doc = "`write(|w| ..)` method takes [`ctr::W`](W) writer structure"]
144impl crate::Writable for CTR_SPEC {
145 type Safety = crate::Unsafe;
146}
147#[doc = "`reset()` method sets CTR to value 0x03"]
148impl crate::Resettable for CTR_SPEC {
149 const RESET_VALUE: u32 = 0x03;
150}