esp32/dport/
pro_dcache_dbug0.rs

1#[doc = "Register `PRO_DCACHE_DBUG0` reader"]
2pub type R = crate::R<PRO_DCACHE_DBUG0_SPEC>;
3#[doc = "Register `PRO_DCACHE_DBUG0` writer"]
4pub type W = crate::W<PRO_DCACHE_DBUG0_SPEC>;
5#[doc = "Field `PRO_SLAVE_WDATA` reader - "]
6pub type PRO_SLAVE_WDATA_R = crate::BitReader;
7#[doc = "Field `PRO_SLAVE_WDATA` writer - "]
8pub type PRO_SLAVE_WDATA_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `PRO_CACHE_MMU_IA` reader - "]
10pub type PRO_CACHE_MMU_IA_R = crate::BitReader;
11#[doc = "Field `PRO_CACHE_IA` reader - "]
12pub type PRO_CACHE_IA_R = crate::FieldReader;
13#[doc = "Field `PRO_CACHE_STATE` reader - "]
14pub type PRO_CACHE_STATE_R = crate::FieldReader<u16>;
15#[doc = "Field `PRO_WR_BAK_TO_READ` reader - "]
16pub type PRO_WR_BAK_TO_READ_R = crate::BitReader;
17#[doc = "Field `PRO_TX_END` reader - "]
18pub type PRO_TX_END_R = crate::BitReader;
19#[doc = "Field `PRO_SLAVE_WR` reader - "]
20pub type PRO_SLAVE_WR_R = crate::BitReader;
21#[doc = "Field `PRO_SLAVE_WDATA_V` reader - "]
22pub type PRO_SLAVE_WDATA_V_R = crate::BitReader;
23#[doc = "Field `PRO_RX_END` reader - "]
24pub type PRO_RX_END_R = crate::BitReader;
25impl R {
26    #[doc = "Bit 0"]
27    #[inline(always)]
28    pub fn pro_slave_wdata(&self) -> PRO_SLAVE_WDATA_R {
29        PRO_SLAVE_WDATA_R::new((self.bits & 1) != 0)
30    }
31    #[doc = "Bit 0"]
32    #[inline(always)]
33    pub fn pro_cache_mmu_ia(&self) -> PRO_CACHE_MMU_IA_R {
34        PRO_CACHE_MMU_IA_R::new((self.bits & 1) != 0)
35    }
36    #[doc = "Bits 1:6"]
37    #[inline(always)]
38    pub fn pro_cache_ia(&self) -> PRO_CACHE_IA_R {
39        PRO_CACHE_IA_R::new(((self.bits >> 1) & 0x3f) as u8)
40    }
41    #[doc = "Bits 7:18"]
42    #[inline(always)]
43    pub fn pro_cache_state(&self) -> PRO_CACHE_STATE_R {
44        PRO_CACHE_STATE_R::new(((self.bits >> 7) & 0x0fff) as u16)
45    }
46    #[doc = "Bit 19"]
47    #[inline(always)]
48    pub fn pro_wr_bak_to_read(&self) -> PRO_WR_BAK_TO_READ_R {
49        PRO_WR_BAK_TO_READ_R::new(((self.bits >> 19) & 1) != 0)
50    }
51    #[doc = "Bit 20"]
52    #[inline(always)]
53    pub fn pro_tx_end(&self) -> PRO_TX_END_R {
54        PRO_TX_END_R::new(((self.bits >> 20) & 1) != 0)
55    }
56    #[doc = "Bit 21"]
57    #[inline(always)]
58    pub fn pro_slave_wr(&self) -> PRO_SLAVE_WR_R {
59        PRO_SLAVE_WR_R::new(((self.bits >> 21) & 1) != 0)
60    }
61    #[doc = "Bit 22"]
62    #[inline(always)]
63    pub fn pro_slave_wdata_v(&self) -> PRO_SLAVE_WDATA_V_R {
64        PRO_SLAVE_WDATA_V_R::new(((self.bits >> 22) & 1) != 0)
65    }
66    #[doc = "Bit 23"]
67    #[inline(always)]
68    pub fn pro_rx_end(&self) -> PRO_RX_END_R {
69        PRO_RX_END_R::new(((self.bits >> 23) & 1) != 0)
70    }
71}
72#[cfg(feature = "impl-register-debug")]
73impl core::fmt::Debug for R {
74    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
75        f.debug_struct("PRO_DCACHE_DBUG0")
76            .field("pro_slave_wdata", &self.pro_slave_wdata())
77            .field("pro_cache_mmu_ia", &self.pro_cache_mmu_ia())
78            .field("pro_cache_ia", &self.pro_cache_ia())
79            .field("pro_cache_state", &self.pro_cache_state())
80            .field("pro_wr_bak_to_read", &self.pro_wr_bak_to_read())
81            .field("pro_tx_end", &self.pro_tx_end())
82            .field("pro_slave_wr", &self.pro_slave_wr())
83            .field("pro_slave_wdata_v", &self.pro_slave_wdata_v())
84            .field("pro_rx_end", &self.pro_rx_end())
85            .finish()
86    }
87}
88impl W {
89    #[doc = "Bit 0"]
90    #[inline(always)]
91    pub fn pro_slave_wdata(&mut self) -> PRO_SLAVE_WDATA_W<PRO_DCACHE_DBUG0_SPEC> {
92        PRO_SLAVE_WDATA_W::new(self, 0)
93    }
94}
95#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`pro_dcache_dbug0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pro_dcache_dbug0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
96pub struct PRO_DCACHE_DBUG0_SPEC;
97impl crate::RegisterSpec for PRO_DCACHE_DBUG0_SPEC {
98    type Ux = u32;
99}
100#[doc = "`read()` method returns [`pro_dcache_dbug0::R`](R) reader structure"]
101impl crate::Readable for PRO_DCACHE_DBUG0_SPEC {}
102#[doc = "`write(|w| ..)` method takes [`pro_dcache_dbug0::W`](W) writer structure"]
103impl crate::Writable for PRO_DCACHE_DBUG0_SPEC {
104    type Safety = crate::Unsafe;
105}
106#[doc = "`reset()` method sets PRO_DCACHE_DBUG0 to value 0"]
107impl crate::Resettable for PRO_DCACHE_DBUG0_SPEC {}
esp32/dport/pro_dcache_dbug0.rs

esp32/dport/
pro_dcache_dbug0.rs
