esp32/dport/
app_dcache_dbug5.rs

1#[doc = "Register `APP_DCACHE_DBUG5` reader"]
2pub type R = crate::R<APP_DCACHE_DBUG5_SPEC>;
3#[doc = "Field `APP_DROM0ADDR0_IA` reader - "]
4pub type APP_DROM0ADDR0_IA_R = crate::FieldReader<u32>;
5impl R {
6    #[doc = "Bits 0:19"]
7    #[inline(always)]
8    pub fn app_drom0addr0_ia(&self) -> APP_DROM0ADDR0_IA_R {
9        APP_DROM0ADDR0_IA_R::new(self.bits & 0x000f_ffff)
10    }
11}
12#[cfg(feature = "impl-register-debug")]
13impl core::fmt::Debug for R {
14    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
15        f.debug_struct("APP_DCACHE_DBUG5")
16            .field("app_drom0addr0_ia", &self.app_drom0addr0_ia())
17            .finish()
18    }
19}
20#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`app_dcache_dbug5::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
21pub struct APP_DCACHE_DBUG5_SPEC;
22impl crate::RegisterSpec for APP_DCACHE_DBUG5_SPEC {
23    type Ux = u32;
24}
25#[doc = "`read()` method returns [`app_dcache_dbug5::R`](R) reader structure"]
26impl crate::Readable for APP_DCACHE_DBUG5_SPEC {}
27#[doc = "`reset()` method sets APP_DCACHE_DBUG5 to value 0"]
28impl crate::Resettable for APP_DCACHE_DBUG5_SPEC {}
esp32/dport/app_dcache_dbug5.rs

esp32/dport/
app_dcache_dbug5.rs
