Module apb_saradc_ctrl 

Structs

APB_SARADC_CTRL_SPEC

You can read this register and get apb_saradc_ctrl::R. You can reset, write, write_with_zero this register using apb_saradc_ctrl::W. You can also modify this register. See API.

Type Aliases

R

Register APB_SARADC_CTRL reader

SARADC_DATA_SAR_SEL_R

Field SARADC_DATA_SAR_SEL reader - 1: sar_sel will be coded by the MSB of the 16-bit output data in this case the resolution should not be larger than 11 bits.

SARADC_DATA_SAR_SEL_W

Field SARADC_DATA_SAR_SEL writer - 1: sar_sel will be coded by the MSB of the 16-bit output data in this case the resolution should not be larger than 11 bits.

SARADC_DATA_TO_I2S_R

Field SARADC_DATA_TO_I2S reader - 1: I2S input data is from SAR ADC (for DMA) 0: I2S input data is from GPIO matrix

SARADC_DATA_TO_I2S_W

Field SARADC_DATA_TO_I2S writer - 1: I2S input data is from SAR ADC (for DMA) 0: I2S input data is from GPIO matrix

SARADC_SAR1_PATT_LEN_R

Field SARADC_SAR1_PATT_LEN reader - 0 ~ 15 means length 1 ~ 16

SARADC_SAR1_PATT_LEN_W

Field SARADC_SAR1_PATT_LEN writer - 0 ~ 15 means length 1 ~ 16

SARADC_SAR1_PATT_P_CLEAR_R

Field SARADC_SAR1_PATT_P_CLEAR reader - clear the pointer of pattern table for DIG ADC1 CTRL

SARADC_SAR1_PATT_P_CLEAR_W

Field SARADC_SAR1_PATT_P_CLEAR writer - clear the pointer of pattern table for DIG ADC1 CTRL

SARADC_SAR2_MUX_R

Field SARADC_SAR2_MUX reader - 1: SAR ADC2 is controlled by DIG ADC2 CTRL 0: SAR ADC2 is controlled by PWDET CTRL

SARADC_SAR2_MUX_W

Field SARADC_SAR2_MUX writer - 1: SAR ADC2 is controlled by DIG ADC2 CTRL 0: SAR ADC2 is controlled by PWDET CTRL

SARADC_SAR2_PATT_LEN_R

Field SARADC_SAR2_PATT_LEN reader - 0 ~ 15 means length 1 ~ 16

SARADC_SAR2_PATT_LEN_W

Field SARADC_SAR2_PATT_LEN writer - 0 ~ 15 means length 1 ~ 16

SARADC_SAR2_PATT_P_CLEAR_R

Field SARADC_SAR2_PATT_P_CLEAR reader - clear the pointer of pattern table for DIG ADC2 CTRL

SARADC_SAR2_PATT_P_CLEAR_W

Field SARADC_SAR2_PATT_P_CLEAR writer - clear the pointer of pattern table for DIG ADC2 CTRL

SARADC_SAR_CLK_DIV_R

Field SARADC_SAR_CLK_DIV reader - SAR clock divider

SARADC_SAR_CLK_DIV_W

Field SARADC_SAR_CLK_DIV writer - SAR clock divider

SARADC_SAR_CLK_GATED_R

Field SARADC_SAR_CLK_GATED reader -

SARADC_SAR_CLK_GATED_W

Field SARADC_SAR_CLK_GATED writer -

SARADC_SAR_SEL_R

Field SARADC_SAR_SEL reader - 0: SAR1 1: SAR2 only work for single SAR mode

SARADC_SAR_SEL_W

Field SARADC_SAR_SEL writer - 0: SAR1 1: SAR2 only work for single SAR mode

SARADC_START_FORCE_R

Field SARADC_START_FORCE reader -

SARADC_START_FORCE_W

Field SARADC_START_FORCE writer -

SARADC_START_R

Field SARADC_START reader -

SARADC_START_W

Field SARADC_START writer -

SARADC_WORK_MODE_R

Field SARADC_WORK_MODE reader - 0: single mode 1: double mode 2: alternate mode

SARADC_WORK_MODE_W

Field SARADC_WORK_MODE writer - 0: single mode 1: double mode 2: alternate mode

W

Register APB_SARADC_CTRL writer