1
  2
  3
  4
  5
  6
  7
  8
  9
 10
 11
 12
 13
 14
 15
 16
 17
 18
 19
 20
 21
 22
 23
 24
 25
 26
 27
 28
 29
 30
 31
 32
 33
 34
 35
 36
 37
 38
 39
 40
 41
 42
 43
 44
 45
 46
 47
 48
 49
 50
 51
 52
 53
 54
 55
 56
 57
 58
 59
 60
 61
 62
 63
 64
 65
 66
 67
 68
 69
 70
 71
 72
 73
 74
 75
 76
 77
 78
 79
 80
 81
 82
 83
 84
 85
 86
 87
 88
 89
 90
 91
 92
 93
 94
 95
 96
 97
 98
 99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142

#[doc = "Reader of register LSCH5_CONF0"]
pub type R = crate::R<u32, super::LSCH5_CONF0>;
#[doc = "Writer for register LSCH5_CONF0"]
pub type W = crate::W<u32, super::LSCH5_CONF0>;
#[doc = "Register LSCH5_CONF0 `reset()`'s with value 0"]
impl crate::ResetValue for super::LSCH5_CONF0 {
    type Type = u32;
    #[inline(always)]
    fn reset_value() -> Self::Type {
        0
    }
}
#[doc = "Reader of field `PARA_UP_LSCH5`"]
pub type PARA_UP_LSCH5_R = crate::R<bool, bool>;
#[doc = "Write proxy for field `PARA_UP_LSCH5`"]
pub struct PARA_UP_LSCH5_W<'a> {
    w: &'a mut W,
}
impl<'a> PARA_UP_LSCH5_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
        self.w
    }
}
#[doc = "Reader of field `IDLE_LV_LSCH5`"]
pub type IDLE_LV_LSCH5_R = crate::R<bool, bool>;
#[doc = "Write proxy for field `IDLE_LV_LSCH5`"]
pub struct IDLE_LV_LSCH5_W<'a> {
    w: &'a mut W,
}
impl<'a> IDLE_LV_LSCH5_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
        self.w
    }
}
#[doc = "Reader of field `SIG_OUT_EN_LSCH5`"]
pub type SIG_OUT_EN_LSCH5_R = crate::R<bool, bool>;
#[doc = "Write proxy for field `SIG_OUT_EN_LSCH5`"]
pub struct SIG_OUT_EN_LSCH5_W<'a> {
    w: &'a mut W,
}
impl<'a> SIG_OUT_EN_LSCH5_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
        self.w
    }
}
#[doc = "Reader of field `TIMER_SEL_LSCH5`"]
pub type TIMER_SEL_LSCH5_R = crate::R<u8, u8>;
#[doc = "Write proxy for field `TIMER_SEL_LSCH5`"]
pub struct TIMER_SEL_LSCH5_W<'a> {
    w: &'a mut W,
}
impl<'a> TIMER_SEL_LSCH5_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub unsafe fn bits(self, value: u8) -> &'a mut W {
        self.w.bits = (self.w.bits & !0x03) | ((value as u32) & 0x03);
        self.w
    }
}
impl R {
    #[doc = "Bit 4"]
    #[inline(always)]
    pub fn para_up_lsch5(&self) -> PARA_UP_LSCH5_R {
        PARA_UP_LSCH5_R::new(((self.bits >> 4) & 0x01) != 0)
    }
    #[doc = "Bit 3"]
    #[inline(always)]
    pub fn idle_lv_lsch5(&self) -> IDLE_LV_LSCH5_R {
        IDLE_LV_LSCH5_R::new(((self.bits >> 3) & 0x01) != 0)
    }
    #[doc = "Bit 2"]
    #[inline(always)]
    pub fn sig_out_en_lsch5(&self) -> SIG_OUT_EN_LSCH5_R {
        SIG_OUT_EN_LSCH5_R::new(((self.bits >> 2) & 0x01) != 0)
    }
    #[doc = "Bits 0:1"]
    #[inline(always)]
    pub fn timer_sel_lsch5(&self) -> TIMER_SEL_LSCH5_R {
        TIMER_SEL_LSCH5_R::new((self.bits & 0x03) as u8)
    }
}
impl W {
    #[doc = "Bit 4"]
    #[inline(always)]
    pub fn para_up_lsch5(&mut self) -> PARA_UP_LSCH5_W {
        PARA_UP_LSCH5_W { w: self }
    }
    #[doc = "Bit 3"]
    #[inline(always)]
    pub fn idle_lv_lsch5(&mut self) -> IDLE_LV_LSCH5_W {
        IDLE_LV_LSCH5_W { w: self }
    }
    #[doc = "Bit 2"]
    #[inline(always)]
    pub fn sig_out_en_lsch5(&mut self) -> SIG_OUT_EN_LSCH5_W {
        SIG_OUT_EN_LSCH5_W { w: self }
    }
    #[doc = "Bits 0:1"]
    #[inline(always)]
    pub fn timer_sel_lsch5(&mut self) -> TIMER_SEL_LSCH5_W {
        TIMER_SEL_LSCH5_W { w: self }
    }
}