1#[doc = "Register `STATUS` reader"]
2pub type R = crate::R<STATUS_SPEC>;
3#[doc = "Field `RXFIFO_CNT` reader - (rx_mem_cnt rxfifo_cnt) stores the byte num of valid datas in receiver's fifo. rx_mem_cnt register stores the 3 most significant bits rxfifo_cnt stores the 8 least significant bits."]
4pub type RXFIFO_CNT_R = crate::FieldReader;
5#[doc = "Field `ST_URX_OUT` reader - This register stores the value of receiver's finite state machine. 0:RX_IDLE 1:RX_STRT 2:RX_DAT0 3:RX_DAT1 4:RX_DAT2 5:RX_DAT3 6:RX_DAT4 7:RX_DAT5 8:RX_DAT6 9:RX_DAT7 10:RX_PRTY 11:RX_STP1 12:RX_STP2 13:RX_DL1"]
6pub type ST_URX_OUT_R = crate::FieldReader;
7#[doc = "Field `DSRN` reader - This register stores the level value of the internal uart dsr signal."]
8pub type DSRN_R = crate::BitReader;
9#[doc = "Field `CTSN` reader - This register stores the level value of the internal uart cts signal."]
10pub type CTSN_R = crate::BitReader;
11#[doc = "Field `RXD` reader - This register stores the level value of the internal uart rxd signal."]
12pub type RXD_R = crate::BitReader;
13#[doc = "Field `TXFIFO_CNT` reader - (tx_mem_cnt txfifo_cnt) stores the byte num of valid datas in transmitter's fifo.tx_mem_cnt stores the 3 most significant bits txfifo_cnt stores the 8 least significant bits."]
14pub type TXFIFO_CNT_R = crate::FieldReader;
15#[doc = "Field `ST_UTX_OUT` reader - This register stores the value of transmitter's finite state machine. 0:TX_IDLE 1:TX_STRT 2:TX_DAT0 3:TX_DAT1 4:TX_DAT2 5:TX_DAT3 6:TX_DAT4 7:TX_DAT5 8:TX_DAT6 9:TX_DAT7 10:TX_PRTY 11:TX_STP1 12:TX_STP2 13:TX_DL0 14:TX_DL1"]
16pub type ST_UTX_OUT_R = crate::FieldReader;
17#[doc = "Field `DTRN` reader - The register represent the level value of the internal uart dsr signal."]
18pub type DTRN_R = crate::BitReader;
19#[doc = "Field `RTSN` reader - This register represent the level value of the internal uart cts signal."]
20pub type RTSN_R = crate::BitReader;
21#[doc = "Field `TXD` reader - This register represent the level value of the internal uart rxd signal."]
22pub type TXD_R = crate::BitReader;
23impl R {
24 #[doc = "Bits 0:7 - (rx_mem_cnt rxfifo_cnt) stores the byte num of valid datas in receiver's fifo. rx_mem_cnt register stores the 3 most significant bits rxfifo_cnt stores the 8 least significant bits."]
25 #[inline(always)]
26 pub fn rxfifo_cnt(&self) -> RXFIFO_CNT_R {
27 RXFIFO_CNT_R::new((self.bits & 0xff) as u8)
28 }
29 #[doc = "Bits 8:11 - This register stores the value of receiver's finite state machine. 0:RX_IDLE 1:RX_STRT 2:RX_DAT0 3:RX_DAT1 4:RX_DAT2 5:RX_DAT3 6:RX_DAT4 7:RX_DAT5 8:RX_DAT6 9:RX_DAT7 10:RX_PRTY 11:RX_STP1 12:RX_STP2 13:RX_DL1"]
30 #[inline(always)]
31 pub fn st_urx_out(&self) -> ST_URX_OUT_R {
32 ST_URX_OUT_R::new(((self.bits >> 8) & 0x0f) as u8)
33 }
34 #[doc = "Bit 13 - This register stores the level value of the internal uart dsr signal."]
35 #[inline(always)]
36 pub fn dsrn(&self) -> DSRN_R {
37 DSRN_R::new(((self.bits >> 13) & 1) != 0)
38 }
39 #[doc = "Bit 14 - This register stores the level value of the internal uart cts signal."]
40 #[inline(always)]
41 pub fn ctsn(&self) -> CTSN_R {
42 CTSN_R::new(((self.bits >> 14) & 1) != 0)
43 }
44 #[doc = "Bit 15 - This register stores the level value of the internal uart rxd signal."]
45 #[inline(always)]
46 pub fn rxd(&self) -> RXD_R {
47 RXD_R::new(((self.bits >> 15) & 1) != 0)
48 }
49 #[doc = "Bits 16:23 - (tx_mem_cnt txfifo_cnt) stores the byte num of valid datas in transmitter's fifo.tx_mem_cnt stores the 3 most significant bits txfifo_cnt stores the 8 least significant bits."]
50 #[inline(always)]
51 pub fn txfifo_cnt(&self) -> TXFIFO_CNT_R {
52 TXFIFO_CNT_R::new(((self.bits >> 16) & 0xff) as u8)
53 }
54 #[doc = "Bits 24:27 - This register stores the value of transmitter's finite state machine. 0:TX_IDLE 1:TX_STRT 2:TX_DAT0 3:TX_DAT1 4:TX_DAT2 5:TX_DAT3 6:TX_DAT4 7:TX_DAT5 8:TX_DAT6 9:TX_DAT7 10:TX_PRTY 11:TX_STP1 12:TX_STP2 13:TX_DL0 14:TX_DL1"]
55 #[inline(always)]
56 pub fn st_utx_out(&self) -> ST_UTX_OUT_R {
57 ST_UTX_OUT_R::new(((self.bits >> 24) & 0x0f) as u8)
58 }
59 #[doc = "Bit 29 - The register represent the level value of the internal uart dsr signal."]
60 #[inline(always)]
61 pub fn dtrn(&self) -> DTRN_R {
62 DTRN_R::new(((self.bits >> 29) & 1) != 0)
63 }
64 #[doc = "Bit 30 - This register represent the level value of the internal uart cts signal."]
65 #[inline(always)]
66 pub fn rtsn(&self) -> RTSN_R {
67 RTSN_R::new(((self.bits >> 30) & 1) != 0)
68 }
69 #[doc = "Bit 31 - This register represent the level value of the internal uart rxd signal."]
70 #[inline(always)]
71 pub fn txd(&self) -> TXD_R {
72 TXD_R::new(((self.bits >> 31) & 1) != 0)
73 }
74}
75#[cfg(feature = "impl-register-debug")]
76impl core::fmt::Debug for R {
77 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
78 f.debug_struct("STATUS")
79 .field("rxfifo_cnt", &self.rxfifo_cnt())
80 .field("st_urx_out", &self.st_urx_out())
81 .field("dsrn", &self.dsrn())
82 .field("ctsn", &self.ctsn())
83 .field("rxd", &self.rxd())
84 .field("txfifo_cnt", &self.txfifo_cnt())
85 .field("st_utx_out", &self.st_utx_out())
86 .field("dtrn", &self.dtrn())
87 .field("rtsn", &self.rtsn())
88 .field("txd", &self.txd())
89 .finish()
90 }
91}
92#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
93pub struct STATUS_SPEC;
94impl crate::RegisterSpec for STATUS_SPEC {
95 type Ux = u32;
96}
97#[doc = "`read()` method returns [`status::R`](R) reader structure"]
98impl crate::Readable for STATUS_SPEC {}
99#[doc = "`reset()` method sets STATUS to value 0"]
100impl crate::Resettable for STATUS_SPEC {}