esp32/spi0/
sram_drd_cmd.rs

1#[doc = "Register `SRAM_DRD_CMD` reader"]
2pub type R = crate::R<SRAM_DRD_CMD_SPEC>;
3#[doc = "Register `SRAM_DRD_CMD` writer"]
4pub type W = crate::W<SRAM_DRD_CMD_SPEC>;
5#[doc = "Field `CACHE_SRAM_USR_RD_CMD_VALUE` reader - For SPI0 When cache mode is enable it is the read command value of command phase for SRAM."]
6pub type CACHE_SRAM_USR_RD_CMD_VALUE_R = crate::FieldReader<u16>;
7#[doc = "Field `CACHE_SRAM_USR_RD_CMD_VALUE` writer - For SPI0 When cache mode is enable it is the read command value of command phase for SRAM."]
8pub type CACHE_SRAM_USR_RD_CMD_VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
9#[doc = "Field `CACHE_SRAM_USR_RD_CMD_BITLEN` reader - For SPI0 When cache mode is enable it is the length in bits of command phase for SRAM. The register value shall be (bit_num-1)."]
10pub type CACHE_SRAM_USR_RD_CMD_BITLEN_R = crate::FieldReader;
11#[doc = "Field `CACHE_SRAM_USR_RD_CMD_BITLEN` writer - For SPI0 When cache mode is enable it is the length in bits of command phase for SRAM. The register value shall be (bit_num-1)."]
12pub type CACHE_SRAM_USR_RD_CMD_BITLEN_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
13impl R {
14    #[doc = "Bits 0:15 - For SPI0 When cache mode is enable it is the read command value of command phase for SRAM."]
15    #[inline(always)]
16    pub fn cache_sram_usr_rd_cmd_value(&self) -> CACHE_SRAM_USR_RD_CMD_VALUE_R {
17        CACHE_SRAM_USR_RD_CMD_VALUE_R::new((self.bits & 0xffff) as u16)
18    }
19    #[doc = "Bits 28:31 - For SPI0 When cache mode is enable it is the length in bits of command phase for SRAM. The register value shall be (bit_num-1)."]
20    #[inline(always)]
21    pub fn cache_sram_usr_rd_cmd_bitlen(&self) -> CACHE_SRAM_USR_RD_CMD_BITLEN_R {
22        CACHE_SRAM_USR_RD_CMD_BITLEN_R::new(((self.bits >> 28) & 0x0f) as u8)
23    }
24}
25#[cfg(feature = "impl-register-debug")]
26impl core::fmt::Debug for R {
27    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
28        f.debug_struct("SRAM_DRD_CMD")
29            .field(
30                "cache_sram_usr_rd_cmd_value",
31                &self.cache_sram_usr_rd_cmd_value(),
32            )
33            .field(
34                "cache_sram_usr_rd_cmd_bitlen",
35                &self.cache_sram_usr_rd_cmd_bitlen(),
36            )
37            .finish()
38    }
39}
40impl W {
41    #[doc = "Bits 0:15 - For SPI0 When cache mode is enable it is the read command value of command phase for SRAM."]
42    #[inline(always)]
43    pub fn cache_sram_usr_rd_cmd_value(
44        &mut self,
45    ) -> CACHE_SRAM_USR_RD_CMD_VALUE_W<SRAM_DRD_CMD_SPEC> {
46        CACHE_SRAM_USR_RD_CMD_VALUE_W::new(self, 0)
47    }
48    #[doc = "Bits 28:31 - For SPI0 When cache mode is enable it is the length in bits of command phase for SRAM. The register value shall be (bit_num-1)."]
49    #[inline(always)]
50    pub fn cache_sram_usr_rd_cmd_bitlen(
51        &mut self,
52    ) -> CACHE_SRAM_USR_RD_CMD_BITLEN_W<SRAM_DRD_CMD_SPEC> {
53        CACHE_SRAM_USR_RD_CMD_BITLEN_W::new(self, 28)
54    }
55}
56#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`sram_drd_cmd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sram_drd_cmd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
57pub struct SRAM_DRD_CMD_SPEC;
58impl crate::RegisterSpec for SRAM_DRD_CMD_SPEC {
59    type Ux = u32;
60}
61#[doc = "`read()` method returns [`sram_drd_cmd::R`](R) reader structure"]
62impl crate::Readable for SRAM_DRD_CMD_SPEC {}
63#[doc = "`write(|w| ..)` method takes [`sram_drd_cmd::W`](W) writer structure"]
64impl crate::Writable for SRAM_DRD_CMD_SPEC {
65    type Safety = crate::Unsafe;
66}
67#[doc = "`reset()` method sets SRAM_DRD_CMD to value 0"]
68impl crate::Resettable for SRAM_DRD_CMD_SPEC {}
esp32/spi0/sram_drd_cmd.rs

esp32/spi0/
sram_drd_cmd.rs
