esp32/rtc_cntl/
timer5.rs

1#[doc = "Register `TIMER5` reader"]
2pub type R = crate::R<TIMER5_SPEC>;
3#[doc = "Register `TIMER5` writer"]
4pub type W = crate::W<TIMER5_SPEC>;
5#[doc = "Field `ULP_CP_SUBTIMER_PREDIV` reader - "]
6pub type ULP_CP_SUBTIMER_PREDIV_R = crate::FieldReader;
7#[doc = "Field `ULP_CP_SUBTIMER_PREDIV` writer - "]
8pub type ULP_CP_SUBTIMER_PREDIV_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
9#[doc = "Field `MIN_SLP_VAL` reader - minimal sleep cycles in slow_clk_rtc"]
10pub type MIN_SLP_VAL_R = crate::FieldReader;
11#[doc = "Field `MIN_SLP_VAL` writer - minimal sleep cycles in slow_clk_rtc"]
12pub type MIN_SLP_VAL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
13#[doc = "Field `RTCMEM_WAIT_TIMER` reader - "]
14pub type RTCMEM_WAIT_TIMER_R = crate::FieldReader<u16>;
15#[doc = "Field `RTCMEM_WAIT_TIMER` writer - "]
16pub type RTCMEM_WAIT_TIMER_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
17#[doc = "Field `RTCMEM_POWERUP_TIMER` reader - "]
18pub type RTCMEM_POWERUP_TIMER_R = crate::FieldReader;
19#[doc = "Field `RTCMEM_POWERUP_TIMER` writer - "]
20pub type RTCMEM_POWERUP_TIMER_W<'a, REG> = crate::FieldWriter<'a, REG, 7>;
21impl R {
22    #[doc = "Bits 0:7"]
23    #[inline(always)]
24    pub fn ulp_cp_subtimer_prediv(&self) -> ULP_CP_SUBTIMER_PREDIV_R {
25        ULP_CP_SUBTIMER_PREDIV_R::new((self.bits & 0xff) as u8)
26    }
27    #[doc = "Bits 8:15 - minimal sleep cycles in slow_clk_rtc"]
28    #[inline(always)]
29    pub fn min_slp_val(&self) -> MIN_SLP_VAL_R {
30        MIN_SLP_VAL_R::new(((self.bits >> 8) & 0xff) as u8)
31    }
32    #[doc = "Bits 16:24"]
33    #[inline(always)]
34    pub fn rtcmem_wait_timer(&self) -> RTCMEM_WAIT_TIMER_R {
35        RTCMEM_WAIT_TIMER_R::new(((self.bits >> 16) & 0x01ff) as u16)
36    }
37    #[doc = "Bits 25:31"]
38    #[inline(always)]
39    pub fn rtcmem_powerup_timer(&self) -> RTCMEM_POWERUP_TIMER_R {
40        RTCMEM_POWERUP_TIMER_R::new(((self.bits >> 25) & 0x7f) as u8)
41    }
42}
43#[cfg(feature = "impl-register-debug")]
44impl core::fmt::Debug for R {
45    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
46        f.debug_struct("TIMER5")
47            .field("ulp_cp_subtimer_prediv", &self.ulp_cp_subtimer_prediv())
48            .field("min_slp_val", &self.min_slp_val())
49            .field("rtcmem_wait_timer", &self.rtcmem_wait_timer())
50            .field("rtcmem_powerup_timer", &self.rtcmem_powerup_timer())
51            .finish()
52    }
53}
54impl W {
55    #[doc = "Bits 0:7"]
56    #[inline(always)]
57    pub fn ulp_cp_subtimer_prediv(&mut self) -> ULP_CP_SUBTIMER_PREDIV_W<TIMER5_SPEC> {
58        ULP_CP_SUBTIMER_PREDIV_W::new(self, 0)
59    }
60    #[doc = "Bits 8:15 - minimal sleep cycles in slow_clk_rtc"]
61    #[inline(always)]
62    pub fn min_slp_val(&mut self) -> MIN_SLP_VAL_W<TIMER5_SPEC> {
63        MIN_SLP_VAL_W::new(self, 8)
64    }
65    #[doc = "Bits 16:24"]
66    #[inline(always)]
67    pub fn rtcmem_wait_timer(&mut self) -> RTCMEM_WAIT_TIMER_W<TIMER5_SPEC> {
68        RTCMEM_WAIT_TIMER_W::new(self, 16)
69    }
70    #[doc = "Bits 25:31"]
71    #[inline(always)]
72    pub fn rtcmem_powerup_timer(&mut self) -> RTCMEM_POWERUP_TIMER_W<TIMER5_SPEC> {
73        RTCMEM_POWERUP_TIMER_W::new(self, 25)
74    }
75}
76#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`timer5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
77pub struct TIMER5_SPEC;
78impl crate::RegisterSpec for TIMER5_SPEC {
79    type Ux = u32;
80}
81#[doc = "`read()` method returns [`timer5::R`](R) reader structure"]
82impl crate::Readable for TIMER5_SPEC {}
83#[doc = "`write(|w| ..)` method takes [`timer5::W`](W) writer structure"]
84impl crate::Writable for TIMER5_SPEC {
85    type Safety = crate::Unsafe;
86}
87#[doc = "`reset()` method sets TIMER5 to value 0x1214_8001"]
88impl crate::Resettable for TIMER5_SPEC {
89    const RESET_VALUE: u32 = 0x1214_8001;
90}
esp32/rtc_cntl/timer5.rs

esp32/rtc_cntl/
timer5.rs
