1#[repr(C)]
2#[cfg_attr(feature = "impl-register-debug", derive(Debug))]
3#[doc = "Register block"]
4pub struct RegisterBlock {
5 clk_cfg: CLK_CFG,
6 timer: [TIMER; 3],
7 timer_synci_cfg: TIMER_SYNCI_CFG,
8 operator_timersel: OPERATOR_TIMERSEL,
9 ch: [CH; 3],
10 fault_detect: FAULT_DETECT,
11 cap_timer_cfg: CAP_TIMER_CFG,
12 cap_timer_phase: CAP_TIMER_PHASE,
13 cap_ch_cfg: [CAP_CH_CFG; 3],
14 cap_ch: [CAP_CH; 3],
15 cap_status: CAP_STATUS,
16 update_cfg: UPDATE_CFG,
17 int_ena: INT_ENA,
18 int_raw: INT_RAW,
19 int_st: INT_ST,
20 int_clr: INT_CLR,
21 clk: CLK,
22 version: VERSION,
23}
24impl RegisterBlock {
25 #[doc = "0x00 - "]
26 #[inline(always)]
27 pub const fn clk_cfg(&self) -> &CLK_CFG {
28 &self.clk_cfg
29 }
30 #[doc = "0x04..0x34 - Cluster TIMER%s, containing TIMER?_CFG0, TIMER?_CFG1, TIMER?_SYNC, TIMER?_STATUS"]
31 #[inline(always)]
32 pub const fn timer(&self, n: usize) -> &TIMER {
33 &self.timer[n]
34 }
35 #[doc = "Iterator for array of:"]
36 #[doc = "0x04..0x34 - Cluster TIMER%s, containing TIMER?_CFG0, TIMER?_CFG1, TIMER?_SYNC, TIMER?_STATUS"]
37 #[inline(always)]
38 pub fn timer_iter(&self) -> impl Iterator<Item = &TIMER> {
39 self.timer.iter()
40 }
41 #[doc = "0x34 - "]
42 #[inline(always)]
43 pub const fn timer_synci_cfg(&self) -> &TIMER_SYNCI_CFG {
44 &self.timer_synci_cfg
45 }
46 #[doc = "0x38 - "]
47 #[inline(always)]
48 pub const fn operator_timersel(&self) -> &OPERATOR_TIMERSEL {
49 &self.operator_timersel
50 }
51 #[doc = "0x3c..0xe4 - Cluster CH%s, containing GEN?_STMP_CFG, GEN?_TSTMP_A, GEN?_TSTMP_B, GEN?_CFG0, GEN?_FORCE, GEN?_A, GEN?_B, DT?_CFG, DT?_FED_CFG, DT?_RED_CFG, CARRIER?_CFG, FH?_CFG0, FH?_CFG1, FH?_STATUS"]
52 #[inline(always)]
53 pub const fn ch(&self, n: usize) -> &CH {
54 &self.ch[n]
55 }
56 #[doc = "Iterator for array of:"]
57 #[doc = "0x3c..0xe4 - Cluster CH%s, containing GEN?_STMP_CFG, GEN?_TSTMP_A, GEN?_TSTMP_B, GEN?_CFG0, GEN?_FORCE, GEN?_A, GEN?_B, DT?_CFG, DT?_FED_CFG, DT?_RED_CFG, CARRIER?_CFG, FH?_CFG0, FH?_CFG1, FH?_STATUS"]
58 #[inline(always)]
59 pub fn ch_iter(&self) -> impl Iterator<Item = &CH> {
60 self.ch.iter()
61 }
62 #[doc = "0xe4 - "]
63 #[inline(always)]
64 pub const fn fault_detect(&self) -> &FAULT_DETECT {
65 &self.fault_detect
66 }
67 #[doc = "0xe8 - "]
68 #[inline(always)]
69 pub const fn cap_timer_cfg(&self) -> &CAP_TIMER_CFG {
70 &self.cap_timer_cfg
71 }
72 #[doc = "0xec - "]
73 #[inline(always)]
74 pub const fn cap_timer_phase(&self) -> &CAP_TIMER_PHASE {
75 &self.cap_timer_phase
76 }
77 #[doc = "0xf0..0xfc - Capture channel %s configuration and enable"]
78 #[inline(always)]
79 pub const fn cap_ch_cfg(&self, n: usize) -> &CAP_CH_CFG {
80 &self.cap_ch_cfg[n]
81 }
82 #[doc = "Iterator for array of:"]
83 #[doc = "0xf0..0xfc - Capture channel %s configuration and enable"]
84 #[inline(always)]
85 pub fn cap_ch_cfg_iter(&self) -> impl Iterator<Item = &CAP_CH_CFG> {
86 self.cap_ch_cfg.iter()
87 }
88 #[doc = "0xf0 - Capture channel 0 configuration and enable"]
89 #[inline(always)]
90 pub const fn cap_ch0_cfg(&self) -> &CAP_CH_CFG {
91 self.cap_ch_cfg(0)
92 }
93 #[doc = "0xf4 - Capture channel 1 configuration and enable"]
94 #[inline(always)]
95 pub const fn cap_ch1_cfg(&self) -> &CAP_CH_CFG {
96 self.cap_ch_cfg(1)
97 }
98 #[doc = "0xf8 - Capture channel 2 configuration and enable"]
99 #[inline(always)]
100 pub const fn cap_ch2_cfg(&self) -> &CAP_CH_CFG {
101 self.cap_ch_cfg(2)
102 }
103 #[doc = "0xfc..0x108 - Value of last capture on channel %s"]
104 #[inline(always)]
105 pub const fn cap_ch(&self, n: usize) -> &CAP_CH {
106 &self.cap_ch[n]
107 }
108 #[doc = "Iterator for array of:"]
109 #[doc = "0xfc..0x108 - Value of last capture on channel %s"]
110 #[inline(always)]
111 pub fn cap_ch_iter(&self) -> impl Iterator<Item = &CAP_CH> {
112 self.cap_ch.iter()
113 }
114 #[doc = "0x108 - "]
115 #[inline(always)]
116 pub const fn cap_status(&self) -> &CAP_STATUS {
117 &self.cap_status
118 }
119 #[doc = "0x10c - "]
120 #[inline(always)]
121 pub const fn update_cfg(&self) -> &UPDATE_CFG {
122 &self.update_cfg
123 }
124 #[doc = "0x110 - "]
125 #[inline(always)]
126 pub const fn int_ena(&self) -> &INT_ENA {
127 &self.int_ena
128 }
129 #[doc = "0x114 - "]
130 #[inline(always)]
131 pub const fn int_raw(&self) -> &INT_RAW {
132 &self.int_raw
133 }
134 #[doc = "0x118 - "]
135 #[inline(always)]
136 pub const fn int_st(&self) -> &INT_ST {
137 &self.int_st
138 }
139 #[doc = "0x11c - "]
140 #[inline(always)]
141 pub const fn int_clr(&self) -> &INT_CLR {
142 &self.int_clr
143 }
144 #[doc = "0x120 - "]
145 #[inline(always)]
146 pub const fn clk(&self) -> &CLK {
147 &self.clk
148 }
149 #[doc = "0x124 - "]
150 #[inline(always)]
151 pub const fn version(&self) -> &VERSION {
152 &self.version
153 }
154}
155#[doc = "CLK_CFG (rw) register accessor: \n\nYou can [`read`](crate::Reg::read) this register and get [`clk_cfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_cfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_cfg`] module"]
156pub type CLK_CFG = crate::Reg<clk_cfg::CLK_CFG_SPEC>;
157#[doc = ""]
158pub mod clk_cfg;
159#[doc = "Cluster TIMER%s, containing TIMER?_CFG0, TIMER?_CFG1, TIMER?_SYNC, TIMER?_STATUS"]
160pub use self::timer::TIMER;
161#[doc = r"Cluster"]
162#[doc = "Cluster TIMER%s, containing TIMER?_CFG0, TIMER?_CFG1, TIMER?_SYNC, TIMER?_STATUS"]
163pub mod timer;
164#[doc = "TIMER_SYNCI_CFG (rw) register accessor: \n\nYou can [`read`](crate::Reg::read) this register and get [`timer_synci_cfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer_synci_cfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timer_synci_cfg`] module"]
165pub type TIMER_SYNCI_CFG = crate::Reg<timer_synci_cfg::TIMER_SYNCI_CFG_SPEC>;
166#[doc = ""]
167pub mod timer_synci_cfg;
168#[doc = "OPERATOR_TIMERSEL (rw) register accessor: \n\nYou can [`read`](crate::Reg::read) this register and get [`operator_timersel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`operator_timersel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@operator_timersel`] module"]
169pub type OPERATOR_TIMERSEL = crate::Reg<operator_timersel::OPERATOR_TIMERSEL_SPEC>;
170#[doc = ""]
171pub mod operator_timersel;
172#[doc = "Cluster CH%s, containing GEN?_STMP_CFG, GEN?_TSTMP_A, GEN?_TSTMP_B, GEN?_CFG0, GEN?_FORCE, GEN?_A, GEN?_B, DT?_CFG, DT?_FED_CFG, DT?_RED_CFG, CARRIER?_CFG, FH?_CFG0, FH?_CFG1, FH?_STATUS"]
173pub use self::ch::CH;
174#[doc = r"Cluster"]
175#[doc = "Cluster CH%s, containing GEN?_STMP_CFG, GEN?_TSTMP_A, GEN?_TSTMP_B, GEN?_CFG0, GEN?_FORCE, GEN?_A, GEN?_B, DT?_CFG, DT?_FED_CFG, DT?_RED_CFG, CARRIER?_CFG, FH?_CFG0, FH?_CFG1, FH?_STATUS"]
176pub mod ch;
177#[doc = "FAULT_DETECT (rw) register accessor: \n\nYou can [`read`](crate::Reg::read) this register and get [`fault_detect::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fault_detect::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fault_detect`] module"]
178pub type FAULT_DETECT = crate::Reg<fault_detect::FAULT_DETECT_SPEC>;
179#[doc = ""]
180pub mod fault_detect;
181#[doc = "CAP_TIMER_CFG (rw) register accessor: \n\nYou can [`read`](crate::Reg::read) this register and get [`cap_timer_cfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cap_timer_cfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cap_timer_cfg`] module"]
182pub type CAP_TIMER_CFG = crate::Reg<cap_timer_cfg::CAP_TIMER_CFG_SPEC>;
183#[doc = ""]
184pub mod cap_timer_cfg;
185#[doc = "CAP_TIMER_PHASE (rw) register accessor: \n\nYou can [`read`](crate::Reg::read) this register and get [`cap_timer_phase::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cap_timer_phase::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cap_timer_phase`] module"]
186pub type CAP_TIMER_PHASE = crate::Reg<cap_timer_phase::CAP_TIMER_PHASE_SPEC>;
187#[doc = ""]
188pub mod cap_timer_phase;
189#[doc = "CAP_CH_CFG (rw) register accessor: Capture channel %s configuration and enable\n\nYou can [`read`](crate::Reg::read) this register and get [`cap_ch_cfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cap_ch_cfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cap_ch_cfg`] module"]
190pub type CAP_CH_CFG = crate::Reg<cap_ch_cfg::CAP_CH_CFG_SPEC>;
191#[doc = "Capture channel %s configuration and enable"]
192pub mod cap_ch_cfg;
193#[doc = "CAP_CH (r) register accessor: Value of last capture on channel %s\n\nYou can [`read`](crate::Reg::read) this register and get [`cap_ch::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cap_ch`] module"]
194pub type CAP_CH = crate::Reg<cap_ch::CAP_CH_SPEC>;
195#[doc = "Value of last capture on channel %s"]
196pub mod cap_ch;
197#[doc = "CAP_STATUS (r) register accessor: \n\nYou can [`read`](crate::Reg::read) this register and get [`cap_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cap_status`] module"]
198pub type CAP_STATUS = crate::Reg<cap_status::CAP_STATUS_SPEC>;
199#[doc = ""]
200pub mod cap_status;
201#[doc = "UPDATE_CFG (rw) register accessor: \n\nYou can [`read`](crate::Reg::read) this register and get [`update_cfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`update_cfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@update_cfg`] module"]
202pub type UPDATE_CFG = crate::Reg<update_cfg::UPDATE_CFG_SPEC>;
203#[doc = ""]
204pub mod update_cfg;
205#[doc = "INT_ENA (rw) register accessor: \n\nYou can [`read`](crate::Reg::read) this register and get [`int_ena::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ena::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ena`] module"]
206pub type INT_ENA = crate::Reg<int_ena::INT_ENA_SPEC>;
207#[doc = ""]
208pub mod int_ena;
209#[doc = "INT_RAW (rw) register accessor: \n\nYou can [`read`](crate::Reg::read) this register and get [`int_raw::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_raw::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_raw`] module"]
210pub type INT_RAW = crate::Reg<int_raw::INT_RAW_SPEC>;
211#[doc = ""]
212pub mod int_raw;
213#[doc = "INT_ST (r) register accessor: \n\nYou can [`read`](crate::Reg::read) this register and get [`int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_st`] module"]
214pub type INT_ST = crate::Reg<int_st::INT_ST_SPEC>;
215#[doc = ""]
216pub mod int_st;
217#[doc = "INT_CLR (w) register accessor: \n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_clr`] module"]
218pub type INT_CLR = crate::Reg<int_clr::INT_CLR_SPEC>;
219#[doc = ""]
220pub mod int_clr;
221#[doc = "CLK (rw) register accessor: \n\nYou can [`read`](crate::Reg::read) this register and get [`clk::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk`] module"]
222pub type CLK = crate::Reg<clk::CLK_SPEC>;
223#[doc = ""]
224pub mod clk;
225#[doc = "VERSION (rw) register accessor: \n\nYou can [`read`](crate::Reg::read) this register and get [`version::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`version::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@version`] module"]
226pub type VERSION = crate::Reg<version::VERSION_SPEC>;
227#[doc = ""]
228pub mod version;