esp32/i2s0/
fifo_conf.rs

1#[doc = "Register `FIFO_CONF` reader"]
2pub type R = crate::R<FIFO_CONF_SPEC>;
3#[doc = "Register `FIFO_CONF` writer"]
4pub type W = crate::W<FIFO_CONF_SPEC>;
5#[doc = "Field `RX_DATA_NUM` reader - "]
6pub type RX_DATA_NUM_R = crate::FieldReader;
7#[doc = "Field `RX_DATA_NUM` writer - "]
8pub type RX_DATA_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
9#[doc = "Field `TX_DATA_NUM` reader - "]
10pub type TX_DATA_NUM_R = crate::FieldReader;
11#[doc = "Field `TX_DATA_NUM` writer - "]
12pub type TX_DATA_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
13#[doc = "Field `DSCR_EN` reader - "]
14pub type DSCR_EN_R = crate::BitReader;
15#[doc = "Field `DSCR_EN` writer - "]
16pub type DSCR_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `TX_FIFO_MOD` reader - "]
18pub type TX_FIFO_MOD_R = crate::FieldReader;
19#[doc = "Field `TX_FIFO_MOD` writer - "]
20pub type TX_FIFO_MOD_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
21#[doc = "Field `RX_FIFO_MOD` reader - "]
22pub type RX_FIFO_MOD_R = crate::FieldReader;
23#[doc = "Field `RX_FIFO_MOD` writer - "]
24pub type RX_FIFO_MOD_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
25#[doc = "Field `TX_FIFO_MOD_FORCE_EN` reader - "]
26pub type TX_FIFO_MOD_FORCE_EN_R = crate::BitReader;
27#[doc = "Field `TX_FIFO_MOD_FORCE_EN` writer - "]
28pub type TX_FIFO_MOD_FORCE_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `RX_FIFO_MOD_FORCE_EN` reader - "]
30pub type RX_FIFO_MOD_FORCE_EN_R = crate::BitReader;
31#[doc = "Field `RX_FIFO_MOD_FORCE_EN` writer - "]
32pub type RX_FIFO_MOD_FORCE_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
33impl R {
34    #[doc = "Bits 0:5"]
35    #[inline(always)]
36    pub fn rx_data_num(&self) -> RX_DATA_NUM_R {
37        RX_DATA_NUM_R::new((self.bits & 0x3f) as u8)
38    }
39    #[doc = "Bits 6:11"]
40    #[inline(always)]
41    pub fn tx_data_num(&self) -> TX_DATA_NUM_R {
42        TX_DATA_NUM_R::new(((self.bits >> 6) & 0x3f) as u8)
43    }
44    #[doc = "Bit 12"]
45    #[inline(always)]
46    pub fn dscr_en(&self) -> DSCR_EN_R {
47        DSCR_EN_R::new(((self.bits >> 12) & 1) != 0)
48    }
49    #[doc = "Bits 13:15"]
50    #[inline(always)]
51    pub fn tx_fifo_mod(&self) -> TX_FIFO_MOD_R {
52        TX_FIFO_MOD_R::new(((self.bits >> 13) & 7) as u8)
53    }
54    #[doc = "Bits 16:18"]
55    #[inline(always)]
56    pub fn rx_fifo_mod(&self) -> RX_FIFO_MOD_R {
57        RX_FIFO_MOD_R::new(((self.bits >> 16) & 7) as u8)
58    }
59    #[doc = "Bit 19"]
60    #[inline(always)]
61    pub fn tx_fifo_mod_force_en(&self) -> TX_FIFO_MOD_FORCE_EN_R {
62        TX_FIFO_MOD_FORCE_EN_R::new(((self.bits >> 19) & 1) != 0)
63    }
64    #[doc = "Bit 20"]
65    #[inline(always)]
66    pub fn rx_fifo_mod_force_en(&self) -> RX_FIFO_MOD_FORCE_EN_R {
67        RX_FIFO_MOD_FORCE_EN_R::new(((self.bits >> 20) & 1) != 0)
68    }
69}
70#[cfg(feature = "impl-register-debug")]
71impl core::fmt::Debug for R {
72    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
73        f.debug_struct("FIFO_CONF")
74            .field("rx_data_num", &self.rx_data_num())
75            .field("tx_data_num", &self.tx_data_num())
76            .field("dscr_en", &self.dscr_en())
77            .field("tx_fifo_mod", &self.tx_fifo_mod())
78            .field("rx_fifo_mod", &self.rx_fifo_mod())
79            .field("tx_fifo_mod_force_en", &self.tx_fifo_mod_force_en())
80            .field("rx_fifo_mod_force_en", &self.rx_fifo_mod_force_en())
81            .finish()
82    }
83}
84impl W {
85    #[doc = "Bits 0:5"]
86    #[inline(always)]
87    pub fn rx_data_num(&mut self) -> RX_DATA_NUM_W<FIFO_CONF_SPEC> {
88        RX_DATA_NUM_W::new(self, 0)
89    }
90    #[doc = "Bits 6:11"]
91    #[inline(always)]
92    pub fn tx_data_num(&mut self) -> TX_DATA_NUM_W<FIFO_CONF_SPEC> {
93        TX_DATA_NUM_W::new(self, 6)
94    }
95    #[doc = "Bit 12"]
96    #[inline(always)]
97    pub fn dscr_en(&mut self) -> DSCR_EN_W<FIFO_CONF_SPEC> {
98        DSCR_EN_W::new(self, 12)
99    }
100    #[doc = "Bits 13:15"]
101    #[inline(always)]
102    pub fn tx_fifo_mod(&mut self) -> TX_FIFO_MOD_W<FIFO_CONF_SPEC> {
103        TX_FIFO_MOD_W::new(self, 13)
104    }
105    #[doc = "Bits 16:18"]
106    #[inline(always)]
107    pub fn rx_fifo_mod(&mut self) -> RX_FIFO_MOD_W<FIFO_CONF_SPEC> {
108        RX_FIFO_MOD_W::new(self, 16)
109    }
110    #[doc = "Bit 19"]
111    #[inline(always)]
112    pub fn tx_fifo_mod_force_en(&mut self) -> TX_FIFO_MOD_FORCE_EN_W<FIFO_CONF_SPEC> {
113        TX_FIFO_MOD_FORCE_EN_W::new(self, 19)
114    }
115    #[doc = "Bit 20"]
116    #[inline(always)]
117    pub fn rx_fifo_mod_force_en(&mut self) -> RX_FIFO_MOD_FORCE_EN_W<FIFO_CONF_SPEC> {
118        RX_FIFO_MOD_FORCE_EN_W::new(self, 20)
119    }
120}
121#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`fifo_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
122pub struct FIFO_CONF_SPEC;
123impl crate::RegisterSpec for FIFO_CONF_SPEC {
124    type Ux = u32;
125}
126#[doc = "`read()` method returns [`fifo_conf::R`](R) reader structure"]
127impl crate::Readable for FIFO_CONF_SPEC {}
128#[doc = "`write(|w| ..)` method takes [`fifo_conf::W`](W) writer structure"]
129impl crate::Writable for FIFO_CONF_SPEC {
130    type Safety = crate::Unsafe;
131}
132#[doc = "`reset()` method sets FIFO_CONF to value 0x1820"]
133impl crate::Resettable for FIFO_CONF_SPEC {
134    const RESET_VALUE: u32 = 0x1820;
135}
esp32/i2s0/fifo_conf.rs

esp32/i2s0/
fifo_conf.rs
