esp32/dport/
wifi_clk_en.rs

1#[doc = "Register `WIFI_CLK_EN` reader"]
2pub type R = crate::R<WIFI_CLK_EN_SPEC>;
3#[doc = "Register `WIFI_CLK_EN` writer"]
4pub type W = crate::W<WIFI_CLK_EN_SPEC>;
5#[doc = "Field `WIFI_CLK_EN` reader - "]
6pub type WIFI_CLK_EN_R = crate::FieldReader<u32>;
7#[doc = "Field `WIFI_CLK_EN` writer - "]
8pub type WIFI_CLK_EN_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
9#[doc = "Field `WIFI_CLK_WIFI_EN` reader - "]
10pub type WIFI_CLK_WIFI_EN_R = crate::FieldReader;
11#[doc = "Field `WIFI_CLK_WIFI_EN` writer - "]
12pub type WIFI_CLK_WIFI_EN_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
13#[doc = "Field `WIFI_CLK_WIFI_BT_COMMON` reader - "]
14pub type WIFI_CLK_WIFI_BT_COMMON_R = crate::FieldReader;
15#[doc = "Field `WIFI_CLK_WIFI_BT_COMMON` writer - "]
16pub type WIFI_CLK_WIFI_BT_COMMON_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
17#[doc = "Field `WIFI_CLK_BT_EN` reader - "]
18pub type WIFI_CLK_BT_EN_R = crate::FieldReader;
19#[doc = "Field `WIFI_CLK_BT_EN` writer - "]
20pub type WIFI_CLK_BT_EN_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
21impl R {
22    #[doc = "Bits 0:31"]
23    #[inline(always)]
24    pub fn wifi_clk_en(&self) -> WIFI_CLK_EN_R {
25        WIFI_CLK_EN_R::new(self.bits)
26    }
27    #[doc = "Bits 0:2"]
28    #[inline(always)]
29    pub fn wifi_clk_wifi_en(&self) -> WIFI_CLK_WIFI_EN_R {
30        WIFI_CLK_WIFI_EN_R::new((self.bits & 7) as u8)
31    }
32    #[doc = "Bits 0:5"]
33    #[inline(always)]
34    pub fn wifi_clk_wifi_bt_common(&self) -> WIFI_CLK_WIFI_BT_COMMON_R {
35        WIFI_CLK_WIFI_BT_COMMON_R::new((self.bits & 0x3f) as u8)
36    }
37    #[doc = "Bits 11:13"]
38    #[inline(always)]
39    pub fn wifi_clk_bt_en(&self) -> WIFI_CLK_BT_EN_R {
40        WIFI_CLK_BT_EN_R::new(((self.bits >> 11) & 7) as u8)
41    }
42}
43#[cfg(feature = "impl-register-debug")]
44impl core::fmt::Debug for R {
45    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
46        f.debug_struct("WIFI_CLK_EN")
47            .field("wifi_clk_en", &self.wifi_clk_en())
48            .field("wifi_clk_wifi_en", &self.wifi_clk_wifi_en())
49            .field("wifi_clk_wifi_bt_common", &self.wifi_clk_wifi_bt_common())
50            .field("wifi_clk_bt_en", &self.wifi_clk_bt_en())
51            .finish()
52    }
53}
54impl W {
55    #[doc = "Bits 0:31"]
56    #[inline(always)]
57    pub fn wifi_clk_en(&mut self) -> WIFI_CLK_EN_W<WIFI_CLK_EN_SPEC> {
58        WIFI_CLK_EN_W::new(self, 0)
59    }
60    #[doc = "Bits 0:2"]
61    #[inline(always)]
62    pub fn wifi_clk_wifi_en(&mut self) -> WIFI_CLK_WIFI_EN_W<WIFI_CLK_EN_SPEC> {
63        WIFI_CLK_WIFI_EN_W::new(self, 0)
64    }
65    #[doc = "Bits 0:5"]
66    #[inline(always)]
67    pub fn wifi_clk_wifi_bt_common(&mut self) -> WIFI_CLK_WIFI_BT_COMMON_W<WIFI_CLK_EN_SPEC> {
68        WIFI_CLK_WIFI_BT_COMMON_W::new(self, 0)
69    }
70    #[doc = "Bits 11:13"]
71    #[inline(always)]
72    pub fn wifi_clk_bt_en(&mut self) -> WIFI_CLK_BT_EN_W<WIFI_CLK_EN_SPEC> {
73        WIFI_CLK_BT_EN_W::new(self, 11)
74    }
75}
76#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`wifi_clk_en::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wifi_clk_en::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
77pub struct WIFI_CLK_EN_SPEC;
78impl crate::RegisterSpec for WIFI_CLK_EN_SPEC {
79    type Ux = u32;
80}
81#[doc = "`read()` method returns [`wifi_clk_en::R`](R) reader structure"]
82impl crate::Readable for WIFI_CLK_EN_SPEC {}
83#[doc = "`write(|w| ..)` method takes [`wifi_clk_en::W`](W) writer structure"]
84impl crate::Writable for WIFI_CLK_EN_SPEC {
85    type Safety = crate::Unsafe;
86}
87#[doc = "`reset()` method sets WIFI_CLK_EN to value 0xfffc_e030"]
88impl crate::Resettable for WIFI_CLK_EN_SPEC {
89    const RESET_VALUE: u32 = 0xfffc_e030;
90}
esp32/dport/wifi_clk_en.rs

esp32/dport/
wifi_clk_en.rs
