1#[doc = "Register `INT_ST` reader"]
2pub type R = crate::R<INT_ST_SPEC>;
3#[doc = "Field `RXFIFO_FULL` reader - This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1."]
4pub type RXFIFO_FULL_R = crate::BitReader;
5#[doc = "Field `TXFIFO_EMPTY` reader - This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1."]
6pub type TXFIFO_EMPTY_R = crate::BitReader;
7#[doc = "Field `PARITY_ERR` reader - This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1."]
8pub type PARITY_ERR_R = crate::BitReader;
9#[doc = "Field `FRM_ERR` reader - This is the status bit for frm_err_int_raw when fm_err_int_ena is set to 1."]
10pub type FRM_ERR_R = crate::BitReader;
11#[doc = "Field `RXFIFO_OVF` reader - This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1."]
12pub type RXFIFO_OVF_R = crate::BitReader;
13#[doc = "Field `DSR_CHG` reader - This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1."]
14pub type DSR_CHG_R = crate::BitReader;
15#[doc = "Field `CTS_CHG` reader - This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1."]
16pub type CTS_CHG_R = crate::BitReader;
17#[doc = "Field `BRK_DET` reader - This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1."]
18pub type BRK_DET_R = crate::BitReader;
19#[doc = "Field `RXFIFO_TOUT` reader - This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1."]
20pub type RXFIFO_TOUT_R = crate::BitReader;
21#[doc = "Field `SW_XON` reader - This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1."]
22pub type SW_XON_R = crate::BitReader;
23#[doc = "Field `SW_XOFF` reader - This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1."]
24pub type SW_XOFF_R = crate::BitReader;
25#[doc = "Field `GLITCH_DET` reader - This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1."]
26pub type GLITCH_DET_R = crate::BitReader;
27#[doc = "Field `TX_BRK_DONE` reader - This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1."]
28pub type TX_BRK_DONE_R = crate::BitReader;
29#[doc = "Field `TX_BRK_IDLE_DONE` reader - This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1."]
30pub type TX_BRK_IDLE_DONE_R = crate::BitReader;
31#[doc = "Field `TX_DONE` reader - This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1."]
32pub type TX_DONE_R = crate::BitReader;
33#[doc = "Field `RS485_PARITY_ERR` reader - This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1."]
34pub type RS485_PARITY_ERR_R = crate::BitReader;
35#[doc = "Field `RS485_FRM_ERR` reader - This is the status bit for rs485_fm_err_int_raw when rs485_fm_err_int_ena is set to 1."]
36pub type RS485_FRM_ERR_R = crate::BitReader;
37#[doc = "Field `RS485_CLASH` reader - This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1."]
38pub type RS485_CLASH_R = crate::BitReader;
39#[doc = "Field `AT_CMD_CHAR_DET` reader - This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1."]
40pub type AT_CMD_CHAR_DET_R = crate::BitReader;
41impl R {
42 #[doc = "Bit 0 - This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1."]
43 #[inline(always)]
44 pub fn rxfifo_full(&self) -> RXFIFO_FULL_R {
45 RXFIFO_FULL_R::new((self.bits & 1) != 0)
46 }
47 #[doc = "Bit 1 - This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1."]
48 #[inline(always)]
49 pub fn txfifo_empty(&self) -> TXFIFO_EMPTY_R {
50 TXFIFO_EMPTY_R::new(((self.bits >> 1) & 1) != 0)
51 }
52 #[doc = "Bit 2 - This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1."]
53 #[inline(always)]
54 pub fn parity_err(&self) -> PARITY_ERR_R {
55 PARITY_ERR_R::new(((self.bits >> 2) & 1) != 0)
56 }
57 #[doc = "Bit 3 - This is the status bit for frm_err_int_raw when fm_err_int_ena is set to 1."]
58 #[inline(always)]
59 pub fn frm_err(&self) -> FRM_ERR_R {
60 FRM_ERR_R::new(((self.bits >> 3) & 1) != 0)
61 }
62 #[doc = "Bit 4 - This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1."]
63 #[inline(always)]
64 pub fn rxfifo_ovf(&self) -> RXFIFO_OVF_R {
65 RXFIFO_OVF_R::new(((self.bits >> 4) & 1) != 0)
66 }
67 #[doc = "Bit 5 - This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1."]
68 #[inline(always)]
69 pub fn dsr_chg(&self) -> DSR_CHG_R {
70 DSR_CHG_R::new(((self.bits >> 5) & 1) != 0)
71 }
72 #[doc = "Bit 6 - This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1."]
73 #[inline(always)]
74 pub fn cts_chg(&self) -> CTS_CHG_R {
75 CTS_CHG_R::new(((self.bits >> 6) & 1) != 0)
76 }
77 #[doc = "Bit 7 - This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1."]
78 #[inline(always)]
79 pub fn brk_det(&self) -> BRK_DET_R {
80 BRK_DET_R::new(((self.bits >> 7) & 1) != 0)
81 }
82 #[doc = "Bit 8 - This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1."]
83 #[inline(always)]
84 pub fn rxfifo_tout(&self) -> RXFIFO_TOUT_R {
85 RXFIFO_TOUT_R::new(((self.bits >> 8) & 1) != 0)
86 }
87 #[doc = "Bit 9 - This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1."]
88 #[inline(always)]
89 pub fn sw_xon(&self) -> SW_XON_R {
90 SW_XON_R::new(((self.bits >> 9) & 1) != 0)
91 }
92 #[doc = "Bit 10 - This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1."]
93 #[inline(always)]
94 pub fn sw_xoff(&self) -> SW_XOFF_R {
95 SW_XOFF_R::new(((self.bits >> 10) & 1) != 0)
96 }
97 #[doc = "Bit 11 - This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1."]
98 #[inline(always)]
99 pub fn glitch_det(&self) -> GLITCH_DET_R {
100 GLITCH_DET_R::new(((self.bits >> 11) & 1) != 0)
101 }
102 #[doc = "Bit 12 - This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1."]
103 #[inline(always)]
104 pub fn tx_brk_done(&self) -> TX_BRK_DONE_R {
105 TX_BRK_DONE_R::new(((self.bits >> 12) & 1) != 0)
106 }
107 #[doc = "Bit 13 - This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1."]
108 #[inline(always)]
109 pub fn tx_brk_idle_done(&self) -> TX_BRK_IDLE_DONE_R {
110 TX_BRK_IDLE_DONE_R::new(((self.bits >> 13) & 1) != 0)
111 }
112 #[doc = "Bit 14 - This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1."]
113 #[inline(always)]
114 pub fn tx_done(&self) -> TX_DONE_R {
115 TX_DONE_R::new(((self.bits >> 14) & 1) != 0)
116 }
117 #[doc = "Bit 15 - This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1."]
118 #[inline(always)]
119 pub fn rs485_parity_err(&self) -> RS485_PARITY_ERR_R {
120 RS485_PARITY_ERR_R::new(((self.bits >> 15) & 1) != 0)
121 }
122 #[doc = "Bit 16 - This is the status bit for rs485_fm_err_int_raw when rs485_fm_err_int_ena is set to 1."]
123 #[inline(always)]
124 pub fn rs485_frm_err(&self) -> RS485_FRM_ERR_R {
125 RS485_FRM_ERR_R::new(((self.bits >> 16) & 1) != 0)
126 }
127 #[doc = "Bit 17 - This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1."]
128 #[inline(always)]
129 pub fn rs485_clash(&self) -> RS485_CLASH_R {
130 RS485_CLASH_R::new(((self.bits >> 17) & 1) != 0)
131 }
132 #[doc = "Bit 18 - This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1."]
133 #[inline(always)]
134 pub fn at_cmd_char_det(&self) -> AT_CMD_CHAR_DET_R {
135 AT_CMD_CHAR_DET_R::new(((self.bits >> 18) & 1) != 0)
136 }
137}
138#[cfg(feature = "impl-register-debug")]
139impl core::fmt::Debug for R {
140 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
141 f.debug_struct("INT_ST")
142 .field("rxfifo_full", &self.rxfifo_full())
143 .field("txfifo_empty", &self.txfifo_empty())
144 .field("parity_err", &self.parity_err())
145 .field("frm_err", &self.frm_err())
146 .field("rxfifo_ovf", &self.rxfifo_ovf())
147 .field("dsr_chg", &self.dsr_chg())
148 .field("cts_chg", &self.cts_chg())
149 .field("brk_det", &self.brk_det())
150 .field("rxfifo_tout", &self.rxfifo_tout())
151 .field("sw_xon", &self.sw_xon())
152 .field("sw_xoff", &self.sw_xoff())
153 .field("glitch_det", &self.glitch_det())
154 .field("tx_brk_done", &self.tx_brk_done())
155 .field("tx_brk_idle_done", &self.tx_brk_idle_done())
156 .field("tx_done", &self.tx_done())
157 .field("rs485_parity_err", &self.rs485_parity_err())
158 .field("rs485_frm_err", &self.rs485_frm_err())
159 .field("rs485_clash", &self.rs485_clash())
160 .field("at_cmd_char_det", &self.at_cmd_char_det())
161 .finish()
162 }
163}
164#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
165pub struct INT_ST_SPEC;
166impl crate::RegisterSpec for INT_ST_SPEC {
167 type Ux = u32;
168}
169#[doc = "`read()` method returns [`int_st::R`](R) reader structure"]
170impl crate::Readable for INT_ST_SPEC {}
171#[doc = "`reset()` method sets INT_ST to value 0"]
172impl crate::Resettable for INT_ST_SPEC {}