esp32/timg0/
lactloadlo.rs

1#[doc = "Register `LACTLOADLO` reader"]
2pub type R = crate::R<LACTLOADLO_SPEC>;
3#[doc = "Register `LACTLOADLO` writer"]
4pub type W = crate::W<LACTLOADLO_SPEC>;
5#[doc = "Field `LOAD_LO` reader - "]
6pub type LOAD_LO_R = crate::FieldReader<u32>;
7#[doc = "Field `LOAD_LO` writer - "]
8pub type LOAD_LO_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
9impl R {
10    #[doc = "Bits 0:31"]
11    #[inline(always)]
12    pub fn load_lo(&self) -> LOAD_LO_R {
13        LOAD_LO_R::new(self.bits)
14    }
15}
16#[cfg(feature = "impl-register-debug")]
17impl core::fmt::Debug for R {
18    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
19        f.debug_struct("LACTLOADLO")
20            .field("load_lo", &self.load_lo())
21            .finish()
22    }
23}
24impl W {
25    #[doc = "Bits 0:31"]
26    #[inline(always)]
27    pub fn load_lo(&mut self) -> LOAD_LO_W<LACTLOADLO_SPEC> {
28        LOAD_LO_W::new(self, 0)
29    }
30}
31#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`lactloadlo::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lactloadlo::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
32pub struct LACTLOADLO_SPEC;
33impl crate::RegisterSpec for LACTLOADLO_SPEC {
34    type Ux = u32;
35}
36#[doc = "`read()` method returns [`lactloadlo::R`](R) reader structure"]
37impl crate::Readable for LACTLOADLO_SPEC {}
38#[doc = "`write(|w| ..)` method takes [`lactloadlo::W`](W) writer structure"]
39impl crate::Writable for LACTLOADLO_SPEC {
40    type Safety = crate::Unsafe;
41}
42#[doc = "`reset()` method sets LACTLOADLO to value 0"]
43impl crate::Resettable for LACTLOADLO_SPEC {}
esp32/timg0/lactloadlo.rs

esp32/timg0/
lactloadlo.rs
