1#[doc = "Register `PIN` reader"]
2pub type R = crate::R<PIN_SPEC>;
3#[doc = "Register `PIN` writer"]
4pub type W = crate::W<PIN_SPEC>;
5#[doc = "Field `CS_DIS(0-2)` reader - Set this bit to raise high SPI_CS%s pin, which means that the SPI device(Ext_RAM(0)/flash(1)) connected to SPI_CS%s is in low level when SPI1 transfer starts"]
6pub type CS_DIS_R = crate::BitReader;
7#[doc = "Field `CS_DIS(0-2)` writer - Set this bit to raise high SPI_CS%s pin, which means that the SPI device(Ext_RAM(0)/flash(1)) connected to SPI_CS%s is in low level when SPI1 transfer starts"]
8pub type CS_DIS_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `CK_DIS` reader - 1: spi clk out disable 0: spi clk out enable"]
10pub type CK_DIS_R = crate::BitReader;
11#[doc = "Field `CK_DIS` writer - 1: spi clk out disable 0: spi clk out enable"]
12pub type CK_DIS_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `MASTER_CS_POL` reader - In the master mode the bits are the polarity of spi cs line the value is equivalent to spi_cs ^ spi_master_cs_pol."]
14pub type MASTER_CS_POL_R = crate::FieldReader;
15#[doc = "Field `MASTER_CS_POL` writer - In the master mode the bits are the polarity of spi cs line the value is equivalent to spi_cs ^ spi_master_cs_pol."]
16pub type MASTER_CS_POL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
17#[doc = "Field `MASTER_CK_SEL` reader - In the master mode spi cs line is enable as spi clk it is combined with spi_cs0_dis spi_cs1_dis spi_cs2_dis."]
18pub type MASTER_CK_SEL_R = crate::FieldReader;
19#[doc = "Field `MASTER_CK_SEL` writer - In the master mode spi cs line is enable as spi clk it is combined with spi_cs0_dis spi_cs1_dis spi_cs2_dis."]
20pub type MASTER_CK_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
21#[doc = "Field `CK_IDLE_EDGE` reader - 1: spi clk line is high when idle 0: spi clk line is low when idle"]
22pub type CK_IDLE_EDGE_R = crate::BitReader;
23#[doc = "Field `CK_IDLE_EDGE` writer - 1: spi clk line is high when idle 0: spi clk line is low when idle"]
24pub type CK_IDLE_EDGE_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `CS_KEEP_ACTIVE` reader - spi cs line keep low when the bit is set."]
26pub type CS_KEEP_ACTIVE_R = crate::BitReader;
27#[doc = "Field `CS_KEEP_ACTIVE` writer - spi cs line keep low when the bit is set."]
28pub type CS_KEEP_ACTIVE_W<'a, REG> = crate::BitWriter<'a, REG>;
29impl R {
30 #[doc = "Set this bit to raise high SPI_CS(0-2) pin, which means that the SPI device(Ext_RAM(0)/flash(1)) connected to SPI_CS(0-2) is in low level when SPI1 transfer starts"]
31 #[doc = ""]
32 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CS0_DIS` field.</div>"]
33 #[inline(always)]
34 pub fn cs_dis(&self, n: u8) -> CS_DIS_R {
35 #[allow(clippy::no_effect)]
36 [(); 3][n as usize];
37 CS_DIS_R::new(((self.bits >> n) & 1) != 0)
38 }
39 #[doc = "Iterator for array of:"]
40 #[doc = "Set this bit to raise high SPI_CS(0-2) pin, which means that the SPI device(Ext_RAM(0)/flash(1)) connected to SPI_CS(0-2) is in low level when SPI1 transfer starts"]
41 #[inline(always)]
42 pub fn cs_dis_iter(&self) -> impl Iterator<Item = CS_DIS_R> + '_ {
43 (0..3).map(move |n| CS_DIS_R::new(((self.bits >> n) & 1) != 0))
44 }
45 #[doc = "Bit 0 - Set this bit to raise high SPI_CS0 pin, which means that the SPI device(Ext_RAM(0)/flash(1)) connected to SPI_CS0 is in low level when SPI1 transfer starts"]
46 #[inline(always)]
47 pub fn cs0_dis(&self) -> CS_DIS_R {
48 CS_DIS_R::new((self.bits & 1) != 0)
49 }
50 #[doc = "Bit 1 - Set this bit to raise high SPI_CS1 pin, which means that the SPI device(Ext_RAM(0)/flash(1)) connected to SPI_CS1 is in low level when SPI1 transfer starts"]
51 #[inline(always)]
52 pub fn cs1_dis(&self) -> CS_DIS_R {
53 CS_DIS_R::new(((self.bits >> 1) & 1) != 0)
54 }
55 #[doc = "Bit 2 - Set this bit to raise high SPI_CS2 pin, which means that the SPI device(Ext_RAM(0)/flash(1)) connected to SPI_CS2 is in low level when SPI1 transfer starts"]
56 #[inline(always)]
57 pub fn cs2_dis(&self) -> CS_DIS_R {
58 CS_DIS_R::new(((self.bits >> 2) & 1) != 0)
59 }
60 #[doc = "Bit 5 - 1: spi clk out disable 0: spi clk out enable"]
61 #[inline(always)]
62 pub fn ck_dis(&self) -> CK_DIS_R {
63 CK_DIS_R::new(((self.bits >> 5) & 1) != 0)
64 }
65 #[doc = "Bits 6:8 - In the master mode the bits are the polarity of spi cs line the value is equivalent to spi_cs ^ spi_master_cs_pol."]
66 #[inline(always)]
67 pub fn master_cs_pol(&self) -> MASTER_CS_POL_R {
68 MASTER_CS_POL_R::new(((self.bits >> 6) & 7) as u8)
69 }
70 #[doc = "Bits 11:13 - In the master mode spi cs line is enable as spi clk it is combined with spi_cs0_dis spi_cs1_dis spi_cs2_dis."]
71 #[inline(always)]
72 pub fn master_ck_sel(&self) -> MASTER_CK_SEL_R {
73 MASTER_CK_SEL_R::new(((self.bits >> 11) & 7) as u8)
74 }
75 #[doc = "Bit 29 - 1: spi clk line is high when idle 0: spi clk line is low when idle"]
76 #[inline(always)]
77 pub fn ck_idle_edge(&self) -> CK_IDLE_EDGE_R {
78 CK_IDLE_EDGE_R::new(((self.bits >> 29) & 1) != 0)
79 }
80 #[doc = "Bit 30 - spi cs line keep low when the bit is set."]
81 #[inline(always)]
82 pub fn cs_keep_active(&self) -> CS_KEEP_ACTIVE_R {
83 CS_KEEP_ACTIVE_R::new(((self.bits >> 30) & 1) != 0)
84 }
85}
86#[cfg(feature = "impl-register-debug")]
87impl core::fmt::Debug for R {
88 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
89 f.debug_struct("PIN")
90 .field("ck_dis", &self.ck_dis())
91 .field("master_cs_pol", &self.master_cs_pol())
92 .field("master_ck_sel", &self.master_ck_sel())
93 .field("ck_idle_edge", &self.ck_idle_edge())
94 .field("cs_keep_active", &self.cs_keep_active())
95 .field("cs0_dis", &self.cs0_dis())
96 .field("cs1_dis", &self.cs1_dis())
97 .field("cs2_dis", &self.cs2_dis())
98 .finish()
99 }
100}
101impl W {
102 #[doc = "Set this bit to raise high SPI_CS(0-2) pin, which means that the SPI device(Ext_RAM(0)/flash(1)) connected to SPI_CS(0-2) is in low level when SPI1 transfer starts"]
103 #[doc = ""]
104 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CS0_DIS` field.</div>"]
105 #[inline(always)]
106 pub fn cs_dis(&mut self, n: u8) -> CS_DIS_W<PIN_SPEC> {
107 #[allow(clippy::no_effect)]
108 [(); 3][n as usize];
109 CS_DIS_W::new(self, n)
110 }
111 #[doc = "Bit 0 - Set this bit to raise high SPI_CS0 pin, which means that the SPI device(Ext_RAM(0)/flash(1)) connected to SPI_CS0 is in low level when SPI1 transfer starts"]
112 #[inline(always)]
113 pub fn cs0_dis(&mut self) -> CS_DIS_W<PIN_SPEC> {
114 CS_DIS_W::new(self, 0)
115 }
116 #[doc = "Bit 1 - Set this bit to raise high SPI_CS1 pin, which means that the SPI device(Ext_RAM(0)/flash(1)) connected to SPI_CS1 is in low level when SPI1 transfer starts"]
117 #[inline(always)]
118 pub fn cs1_dis(&mut self) -> CS_DIS_W<PIN_SPEC> {
119 CS_DIS_W::new(self, 1)
120 }
121 #[doc = "Bit 2 - Set this bit to raise high SPI_CS2 pin, which means that the SPI device(Ext_RAM(0)/flash(1)) connected to SPI_CS2 is in low level when SPI1 transfer starts"]
122 #[inline(always)]
123 pub fn cs2_dis(&mut self) -> CS_DIS_W<PIN_SPEC> {
124 CS_DIS_W::new(self, 2)
125 }
126 #[doc = "Bit 5 - 1: spi clk out disable 0: spi clk out enable"]
127 #[inline(always)]
128 pub fn ck_dis(&mut self) -> CK_DIS_W<PIN_SPEC> {
129 CK_DIS_W::new(self, 5)
130 }
131 #[doc = "Bits 6:8 - In the master mode the bits are the polarity of spi cs line the value is equivalent to spi_cs ^ spi_master_cs_pol."]
132 #[inline(always)]
133 pub fn master_cs_pol(&mut self) -> MASTER_CS_POL_W<PIN_SPEC> {
134 MASTER_CS_POL_W::new(self, 6)
135 }
136 #[doc = "Bits 11:13 - In the master mode spi cs line is enable as spi clk it is combined with spi_cs0_dis spi_cs1_dis spi_cs2_dis."]
137 #[inline(always)]
138 pub fn master_ck_sel(&mut self) -> MASTER_CK_SEL_W<PIN_SPEC> {
139 MASTER_CK_SEL_W::new(self, 11)
140 }
141 #[doc = "Bit 29 - 1: spi clk line is high when idle 0: spi clk line is low when idle"]
142 #[inline(always)]
143 pub fn ck_idle_edge(&mut self) -> CK_IDLE_EDGE_W<PIN_SPEC> {
144 CK_IDLE_EDGE_W::new(self, 29)
145 }
146 #[doc = "Bit 30 - spi cs line keep low when the bit is set."]
147 #[inline(always)]
148 pub fn cs_keep_active(&mut self) -> CS_KEEP_ACTIVE_W<PIN_SPEC> {
149 CS_KEEP_ACTIVE_W::new(self, 30)
150 }
151}
152#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`pin::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pin::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
153pub struct PIN_SPEC;
154impl crate::RegisterSpec for PIN_SPEC {
155 type Ux = u32;
156}
157#[doc = "`read()` method returns [`pin::R`](R) reader structure"]
158impl crate::Readable for PIN_SPEC {}
159#[doc = "`write(|w| ..)` method takes [`pin::W`](W) writer structure"]
160impl crate::Writable for PIN_SPEC {
161 type Safety = crate::Unsafe;
162}
163#[doc = "`reset()` method sets PIN to value 0x06"]
164impl crate::Resettable for PIN_SPEC {
165 const RESET_VALUE: u32 = 0x06;
166}