esp32/slc/
bridge_conf.rs

1#[doc = "Register `BRIDGE_CONF` reader"]
2pub type R = crate::R<BRIDGE_CONF_SPEC>;
3#[doc = "Register `BRIDGE_CONF` writer"]
4pub type W = crate::W<BRIDGE_CONF_SPEC>;
5#[doc = "Field `TXEOF_ENA` reader - "]
6pub type TXEOF_ENA_R = crate::FieldReader;
7#[doc = "Field `TXEOF_ENA` writer - "]
8pub type TXEOF_ENA_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
9#[doc = "Field `FIFO_MAP_ENA` reader - "]
10pub type FIFO_MAP_ENA_R = crate::FieldReader;
11#[doc = "Field `FIFO_MAP_ENA` writer - "]
12pub type FIFO_MAP_ENA_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
13#[doc = "Field `SLC0_TX_DUMMY_MODE` reader - "]
14pub type SLC0_TX_DUMMY_MODE_R = crate::BitReader;
15#[doc = "Field `SLC0_TX_DUMMY_MODE` writer - "]
16pub type SLC0_TX_DUMMY_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `HDA_MAP_128K` reader - "]
18pub type HDA_MAP_128K_R = crate::BitReader;
19#[doc = "Field `HDA_MAP_128K` writer - "]
20pub type HDA_MAP_128K_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `SLC1_TX_DUMMY_MODE` reader - "]
22pub type SLC1_TX_DUMMY_MODE_R = crate::BitReader;
23#[doc = "Field `SLC1_TX_DUMMY_MODE` writer - "]
24pub type SLC1_TX_DUMMY_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `TX_PUSH_IDLE_NUM` reader - "]
26pub type TX_PUSH_IDLE_NUM_R = crate::FieldReader<u16>;
27#[doc = "Field `TX_PUSH_IDLE_NUM` writer - "]
28pub type TX_PUSH_IDLE_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
29impl R {
30    #[doc = "Bits 0:5"]
31    #[inline(always)]
32    pub fn txeof_ena(&self) -> TXEOF_ENA_R {
33        TXEOF_ENA_R::new((self.bits & 0x3f) as u8)
34    }
35    #[doc = "Bits 8:11"]
36    #[inline(always)]
37    pub fn fifo_map_ena(&self) -> FIFO_MAP_ENA_R {
38        FIFO_MAP_ENA_R::new(((self.bits >> 8) & 0x0f) as u8)
39    }
40    #[doc = "Bit 12"]
41    #[inline(always)]
42    pub fn slc0_tx_dummy_mode(&self) -> SLC0_TX_DUMMY_MODE_R {
43        SLC0_TX_DUMMY_MODE_R::new(((self.bits >> 12) & 1) != 0)
44    }
45    #[doc = "Bit 13"]
46    #[inline(always)]
47    pub fn hda_map_128k(&self) -> HDA_MAP_128K_R {
48        HDA_MAP_128K_R::new(((self.bits >> 13) & 1) != 0)
49    }
50    #[doc = "Bit 14"]
51    #[inline(always)]
52    pub fn slc1_tx_dummy_mode(&self) -> SLC1_TX_DUMMY_MODE_R {
53        SLC1_TX_DUMMY_MODE_R::new(((self.bits >> 14) & 1) != 0)
54    }
55    #[doc = "Bits 16:31"]
56    #[inline(always)]
57    pub fn tx_push_idle_num(&self) -> TX_PUSH_IDLE_NUM_R {
58        TX_PUSH_IDLE_NUM_R::new(((self.bits >> 16) & 0xffff) as u16)
59    }
60}
61#[cfg(feature = "impl-register-debug")]
62impl core::fmt::Debug for R {
63    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
64        f.debug_struct("BRIDGE_CONF")
65            .field("txeof_ena", &self.txeof_ena())
66            .field("fifo_map_ena", &self.fifo_map_ena())
67            .field("slc0_tx_dummy_mode", &self.slc0_tx_dummy_mode())
68            .field("hda_map_128k", &self.hda_map_128k())
69            .field("slc1_tx_dummy_mode", &self.slc1_tx_dummy_mode())
70            .field("tx_push_idle_num", &self.tx_push_idle_num())
71            .finish()
72    }
73}
74impl W {
75    #[doc = "Bits 0:5"]
76    #[inline(always)]
77    pub fn txeof_ena(&mut self) -> TXEOF_ENA_W<BRIDGE_CONF_SPEC> {
78        TXEOF_ENA_W::new(self, 0)
79    }
80    #[doc = "Bits 8:11"]
81    #[inline(always)]
82    pub fn fifo_map_ena(&mut self) -> FIFO_MAP_ENA_W<BRIDGE_CONF_SPEC> {
83        FIFO_MAP_ENA_W::new(self, 8)
84    }
85    #[doc = "Bit 12"]
86    #[inline(always)]
87    pub fn slc0_tx_dummy_mode(&mut self) -> SLC0_TX_DUMMY_MODE_W<BRIDGE_CONF_SPEC> {
88        SLC0_TX_DUMMY_MODE_W::new(self, 12)
89    }
90    #[doc = "Bit 13"]
91    #[inline(always)]
92    pub fn hda_map_128k(&mut self) -> HDA_MAP_128K_W<BRIDGE_CONF_SPEC> {
93        HDA_MAP_128K_W::new(self, 13)
94    }
95    #[doc = "Bit 14"]
96    #[inline(always)]
97    pub fn slc1_tx_dummy_mode(&mut self) -> SLC1_TX_DUMMY_MODE_W<BRIDGE_CONF_SPEC> {
98        SLC1_TX_DUMMY_MODE_W::new(self, 14)
99    }
100    #[doc = "Bits 16:31"]
101    #[inline(always)]
102    pub fn tx_push_idle_num(&mut self) -> TX_PUSH_IDLE_NUM_W<BRIDGE_CONF_SPEC> {
103        TX_PUSH_IDLE_NUM_W::new(self, 16)
104    }
105}
106#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`bridge_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bridge_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
107pub struct BRIDGE_CONF_SPEC;
108impl crate::RegisterSpec for BRIDGE_CONF_SPEC {
109    type Ux = u32;
110}
111#[doc = "`read()` method returns [`bridge_conf::R`](R) reader structure"]
112impl crate::Readable for BRIDGE_CONF_SPEC {}
113#[doc = "`write(|w| ..)` method takes [`bridge_conf::W`](W) writer structure"]
114impl crate::Writable for BRIDGE_CONF_SPEC {
115    type Safety = crate::Unsafe;
116}
117#[doc = "`reset()` method sets BRIDGE_CONF to value 0x000a_7720"]
118impl crate::Resettable for BRIDGE_CONF_SPEC {
119    const RESET_VALUE: u32 = 0x000a_7720;
120}
esp32/slc/bridge_conf.rs

esp32/slc/
bridge_conf.rs
