1#[doc = "Register `_0INT_ST` reader"]
2pub type R = crate::R<_0INT_ST_SPEC>;
3#[doc = "Field `FRHOST_BIT0_INT_ST` reader - "]
4pub type FRHOST_BIT0_INT_ST_R = crate::BitReader;
5#[doc = "Field `FRHOST_BIT1_INT_ST` reader - "]
6pub type FRHOST_BIT1_INT_ST_R = crate::BitReader;
7#[doc = "Field `FRHOST_BIT2_INT_ST` reader - "]
8pub type FRHOST_BIT2_INT_ST_R = crate::BitReader;
9#[doc = "Field `FRHOST_BIT3_INT_ST` reader - "]
10pub type FRHOST_BIT3_INT_ST_R = crate::BitReader;
11#[doc = "Field `FRHOST_BIT4_INT_ST` reader - "]
12pub type FRHOST_BIT4_INT_ST_R = crate::BitReader;
13#[doc = "Field `FRHOST_BIT5_INT_ST` reader - "]
14pub type FRHOST_BIT5_INT_ST_R = crate::BitReader;
15#[doc = "Field `FRHOST_BIT6_INT_ST` reader - "]
16pub type FRHOST_BIT6_INT_ST_R = crate::BitReader;
17#[doc = "Field `FRHOST_BIT7_INT_ST` reader - "]
18pub type FRHOST_BIT7_INT_ST_R = crate::BitReader;
19#[doc = "Field `SLC0_RX_START_INT_ST` reader - "]
20pub type SLC0_RX_START_INT_ST_R = crate::BitReader;
21#[doc = "Field `SLC0_TX_START_INT_ST` reader - "]
22pub type SLC0_TX_START_INT_ST_R = crate::BitReader;
23#[doc = "Field `SLC0_RX_UDF_INT_ST` reader - "]
24pub type SLC0_RX_UDF_INT_ST_R = crate::BitReader;
25#[doc = "Field `SLC0_TX_OVF_INT_ST` reader - "]
26pub type SLC0_TX_OVF_INT_ST_R = crate::BitReader;
27#[doc = "Field `SLC0_TOKEN0_1TO0_INT_ST` reader - "]
28pub type SLC0_TOKEN0_1TO0_INT_ST_R = crate::BitReader;
29#[doc = "Field `SLC0_TOKEN1_1TO0_INT_ST` reader - "]
30pub type SLC0_TOKEN1_1TO0_INT_ST_R = crate::BitReader;
31#[doc = "Field `SLC0_TX_DONE_INT_ST` reader - "]
32pub type SLC0_TX_DONE_INT_ST_R = crate::BitReader;
33#[doc = "Field `SLC0_TX_SUC_EOF_INT_ST` reader - "]
34pub type SLC0_TX_SUC_EOF_INT_ST_R = crate::BitReader;
35#[doc = "Field `SLC0_RX_DONE_INT_ST` reader - "]
36pub type SLC0_RX_DONE_INT_ST_R = crate::BitReader;
37#[doc = "Field `SLC0_RX_EOF_INT_ST` reader - "]
38pub type SLC0_RX_EOF_INT_ST_R = crate::BitReader;
39#[doc = "Field `SLC0_TOHOST_INT_ST` reader - "]
40pub type SLC0_TOHOST_INT_ST_R = crate::BitReader;
41#[doc = "Field `SLC0_TX_DSCR_ERR_INT_ST` reader - "]
42pub type SLC0_TX_DSCR_ERR_INT_ST_R = crate::BitReader;
43#[doc = "Field `SLC0_RX_DSCR_ERR_INT_ST` reader - "]
44pub type SLC0_RX_DSCR_ERR_INT_ST_R = crate::BitReader;
45#[doc = "Field `SLC0_TX_DSCR_EMPTY_INT_ST` reader - "]
46pub type SLC0_TX_DSCR_EMPTY_INT_ST_R = crate::BitReader;
47#[doc = "Field `SLC0_HOST_RD_ACK_INT_ST` reader - "]
48pub type SLC0_HOST_RD_ACK_INT_ST_R = crate::BitReader;
49#[doc = "Field `SLC0_WR_RETRY_DONE_INT_ST` reader - "]
50pub type SLC0_WR_RETRY_DONE_INT_ST_R = crate::BitReader;
51#[doc = "Field `SLC0_TX_ERR_EOF_INT_ST` reader - "]
52pub type SLC0_TX_ERR_EOF_INT_ST_R = crate::BitReader;
53#[doc = "Field `CMD_DTC_INT_ST` reader - "]
54pub type CMD_DTC_INT_ST_R = crate::BitReader;
55#[doc = "Field `SLC0_RX_QUICK_EOF_INT_ST` reader - "]
56pub type SLC0_RX_QUICK_EOF_INT_ST_R = crate::BitReader;
57impl R {
58 #[doc = "Bit 0"]
59 #[inline(always)]
60 pub fn frhost_bit0_int_st(&self) -> FRHOST_BIT0_INT_ST_R {
61 FRHOST_BIT0_INT_ST_R::new((self.bits & 1) != 0)
62 }
63 #[doc = "Bit 1"]
64 #[inline(always)]
65 pub fn frhost_bit1_int_st(&self) -> FRHOST_BIT1_INT_ST_R {
66 FRHOST_BIT1_INT_ST_R::new(((self.bits >> 1) & 1) != 0)
67 }
68 #[doc = "Bit 2"]
69 #[inline(always)]
70 pub fn frhost_bit2_int_st(&self) -> FRHOST_BIT2_INT_ST_R {
71 FRHOST_BIT2_INT_ST_R::new(((self.bits >> 2) & 1) != 0)
72 }
73 #[doc = "Bit 3"]
74 #[inline(always)]
75 pub fn frhost_bit3_int_st(&self) -> FRHOST_BIT3_INT_ST_R {
76 FRHOST_BIT3_INT_ST_R::new(((self.bits >> 3) & 1) != 0)
77 }
78 #[doc = "Bit 4"]
79 #[inline(always)]
80 pub fn frhost_bit4_int_st(&self) -> FRHOST_BIT4_INT_ST_R {
81 FRHOST_BIT4_INT_ST_R::new(((self.bits >> 4) & 1) != 0)
82 }
83 #[doc = "Bit 5"]
84 #[inline(always)]
85 pub fn frhost_bit5_int_st(&self) -> FRHOST_BIT5_INT_ST_R {
86 FRHOST_BIT5_INT_ST_R::new(((self.bits >> 5) & 1) != 0)
87 }
88 #[doc = "Bit 6"]
89 #[inline(always)]
90 pub fn frhost_bit6_int_st(&self) -> FRHOST_BIT6_INT_ST_R {
91 FRHOST_BIT6_INT_ST_R::new(((self.bits >> 6) & 1) != 0)
92 }
93 #[doc = "Bit 7"]
94 #[inline(always)]
95 pub fn frhost_bit7_int_st(&self) -> FRHOST_BIT7_INT_ST_R {
96 FRHOST_BIT7_INT_ST_R::new(((self.bits >> 7) & 1) != 0)
97 }
98 #[doc = "Bit 8"]
99 #[inline(always)]
100 pub fn slc0_rx_start_int_st(&self) -> SLC0_RX_START_INT_ST_R {
101 SLC0_RX_START_INT_ST_R::new(((self.bits >> 8) & 1) != 0)
102 }
103 #[doc = "Bit 9"]
104 #[inline(always)]
105 pub fn slc0_tx_start_int_st(&self) -> SLC0_TX_START_INT_ST_R {
106 SLC0_TX_START_INT_ST_R::new(((self.bits >> 9) & 1) != 0)
107 }
108 #[doc = "Bit 10"]
109 #[inline(always)]
110 pub fn slc0_rx_udf_int_st(&self) -> SLC0_RX_UDF_INT_ST_R {
111 SLC0_RX_UDF_INT_ST_R::new(((self.bits >> 10) & 1) != 0)
112 }
113 #[doc = "Bit 11"]
114 #[inline(always)]
115 pub fn slc0_tx_ovf_int_st(&self) -> SLC0_TX_OVF_INT_ST_R {
116 SLC0_TX_OVF_INT_ST_R::new(((self.bits >> 11) & 1) != 0)
117 }
118 #[doc = "Bit 12"]
119 #[inline(always)]
120 pub fn slc0_token0_1to0_int_st(&self) -> SLC0_TOKEN0_1TO0_INT_ST_R {
121 SLC0_TOKEN0_1TO0_INT_ST_R::new(((self.bits >> 12) & 1) != 0)
122 }
123 #[doc = "Bit 13"]
124 #[inline(always)]
125 pub fn slc0_token1_1to0_int_st(&self) -> SLC0_TOKEN1_1TO0_INT_ST_R {
126 SLC0_TOKEN1_1TO0_INT_ST_R::new(((self.bits >> 13) & 1) != 0)
127 }
128 #[doc = "Bit 14"]
129 #[inline(always)]
130 pub fn slc0_tx_done_int_st(&self) -> SLC0_TX_DONE_INT_ST_R {
131 SLC0_TX_DONE_INT_ST_R::new(((self.bits >> 14) & 1) != 0)
132 }
133 #[doc = "Bit 15"]
134 #[inline(always)]
135 pub fn slc0_tx_suc_eof_int_st(&self) -> SLC0_TX_SUC_EOF_INT_ST_R {
136 SLC0_TX_SUC_EOF_INT_ST_R::new(((self.bits >> 15) & 1) != 0)
137 }
138 #[doc = "Bit 16"]
139 #[inline(always)]
140 pub fn slc0_rx_done_int_st(&self) -> SLC0_RX_DONE_INT_ST_R {
141 SLC0_RX_DONE_INT_ST_R::new(((self.bits >> 16) & 1) != 0)
142 }
143 #[doc = "Bit 17"]
144 #[inline(always)]
145 pub fn slc0_rx_eof_int_st(&self) -> SLC0_RX_EOF_INT_ST_R {
146 SLC0_RX_EOF_INT_ST_R::new(((self.bits >> 17) & 1) != 0)
147 }
148 #[doc = "Bit 18"]
149 #[inline(always)]
150 pub fn slc0_tohost_int_st(&self) -> SLC0_TOHOST_INT_ST_R {
151 SLC0_TOHOST_INT_ST_R::new(((self.bits >> 18) & 1) != 0)
152 }
153 #[doc = "Bit 19"]
154 #[inline(always)]
155 pub fn slc0_tx_dscr_err_int_st(&self) -> SLC0_TX_DSCR_ERR_INT_ST_R {
156 SLC0_TX_DSCR_ERR_INT_ST_R::new(((self.bits >> 19) & 1) != 0)
157 }
158 #[doc = "Bit 20"]
159 #[inline(always)]
160 pub fn slc0_rx_dscr_err_int_st(&self) -> SLC0_RX_DSCR_ERR_INT_ST_R {
161 SLC0_RX_DSCR_ERR_INT_ST_R::new(((self.bits >> 20) & 1) != 0)
162 }
163 #[doc = "Bit 21"]
164 #[inline(always)]
165 pub fn slc0_tx_dscr_empty_int_st(&self) -> SLC0_TX_DSCR_EMPTY_INT_ST_R {
166 SLC0_TX_DSCR_EMPTY_INT_ST_R::new(((self.bits >> 21) & 1) != 0)
167 }
168 #[doc = "Bit 22"]
169 #[inline(always)]
170 pub fn slc0_host_rd_ack_int_st(&self) -> SLC0_HOST_RD_ACK_INT_ST_R {
171 SLC0_HOST_RD_ACK_INT_ST_R::new(((self.bits >> 22) & 1) != 0)
172 }
173 #[doc = "Bit 23"]
174 #[inline(always)]
175 pub fn slc0_wr_retry_done_int_st(&self) -> SLC0_WR_RETRY_DONE_INT_ST_R {
176 SLC0_WR_RETRY_DONE_INT_ST_R::new(((self.bits >> 23) & 1) != 0)
177 }
178 #[doc = "Bit 24"]
179 #[inline(always)]
180 pub fn slc0_tx_err_eof_int_st(&self) -> SLC0_TX_ERR_EOF_INT_ST_R {
181 SLC0_TX_ERR_EOF_INT_ST_R::new(((self.bits >> 24) & 1) != 0)
182 }
183 #[doc = "Bit 25"]
184 #[inline(always)]
185 pub fn cmd_dtc_int_st(&self) -> CMD_DTC_INT_ST_R {
186 CMD_DTC_INT_ST_R::new(((self.bits >> 25) & 1) != 0)
187 }
188 #[doc = "Bit 26"]
189 #[inline(always)]
190 pub fn slc0_rx_quick_eof_int_st(&self) -> SLC0_RX_QUICK_EOF_INT_ST_R {
191 SLC0_RX_QUICK_EOF_INT_ST_R::new(((self.bits >> 26) & 1) != 0)
192 }
193}
194#[cfg(feature = "impl-register-debug")]
195impl core::fmt::Debug for R {
196 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
197 f.debug_struct("_0INT_ST")
198 .field("frhost_bit0_int_st", &self.frhost_bit0_int_st())
199 .field("frhost_bit1_int_st", &self.frhost_bit1_int_st())
200 .field("frhost_bit2_int_st", &self.frhost_bit2_int_st())
201 .field("frhost_bit3_int_st", &self.frhost_bit3_int_st())
202 .field("frhost_bit4_int_st", &self.frhost_bit4_int_st())
203 .field("frhost_bit5_int_st", &self.frhost_bit5_int_st())
204 .field("frhost_bit6_int_st", &self.frhost_bit6_int_st())
205 .field("frhost_bit7_int_st", &self.frhost_bit7_int_st())
206 .field("slc0_rx_start_int_st", &self.slc0_rx_start_int_st())
207 .field("slc0_tx_start_int_st", &self.slc0_tx_start_int_st())
208 .field("slc0_rx_udf_int_st", &self.slc0_rx_udf_int_st())
209 .field("slc0_tx_ovf_int_st", &self.slc0_tx_ovf_int_st())
210 .field("slc0_token0_1to0_int_st", &self.slc0_token0_1to0_int_st())
211 .field("slc0_token1_1to0_int_st", &self.slc0_token1_1to0_int_st())
212 .field("slc0_tx_done_int_st", &self.slc0_tx_done_int_st())
213 .field("slc0_tx_suc_eof_int_st", &self.slc0_tx_suc_eof_int_st())
214 .field("slc0_rx_done_int_st", &self.slc0_rx_done_int_st())
215 .field("slc0_rx_eof_int_st", &self.slc0_rx_eof_int_st())
216 .field("slc0_tohost_int_st", &self.slc0_tohost_int_st())
217 .field("slc0_tx_dscr_err_int_st", &self.slc0_tx_dscr_err_int_st())
218 .field("slc0_rx_dscr_err_int_st", &self.slc0_rx_dscr_err_int_st())
219 .field(
220 "slc0_tx_dscr_empty_int_st",
221 &self.slc0_tx_dscr_empty_int_st(),
222 )
223 .field("slc0_host_rd_ack_int_st", &self.slc0_host_rd_ack_int_st())
224 .field(
225 "slc0_wr_retry_done_int_st",
226 &self.slc0_wr_retry_done_int_st(),
227 )
228 .field("slc0_tx_err_eof_int_st", &self.slc0_tx_err_eof_int_st())
229 .field("cmd_dtc_int_st", &self.cmd_dtc_int_st())
230 .field("slc0_rx_quick_eof_int_st", &self.slc0_rx_quick_eof_int_st())
231 .finish()
232 }
233}
234#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`_0int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
235pub struct _0INT_ST_SPEC;
236impl crate::RegisterSpec for _0INT_ST_SPEC {
237 type Ux = u32;
238}
239#[doc = "`read()` method returns [`_0int_st::R`](R) reader structure"]
240impl crate::Readable for _0INT_ST_SPEC {}
241#[doc = "`reset()` method sets _0INT_ST to value 0"]
242impl crate::Resettable for _0INT_ST_SPEC {}