esp32/sdhost/
clksrc.rs

1#[doc = "Register `CLKSRC` reader"]
2pub type R = crate::R<CLKSRC_SPEC>;
3#[doc = "Register `CLKSRC` writer"]
4pub type W = crate::W<CLKSRC_SPEC>;
5#[doc = "Field `CLKSRC` reader - Clock divider source for two SD cards is supported. Each card has two bits assigned to it. For example, bit\\[1:0\\] are assigned for card 0, bit\\[3:2\\] are assigned for card 1. Card 0 maps and internally routes clock divider\\[0:3\\] outputs to cclk_out\\[1:0\\] pins, depending on bit value. 00 : Clock divider 0; 01 : Clock divider 1; 10 : Clock divider 2; 11 : Clock divider 3."]
6pub type CLKSRC_R = crate::FieldReader;
7#[doc = "Field `CLKSRC` writer - Clock divider source for two SD cards is supported. Each card has two bits assigned to it. For example, bit\\[1:0\\] are assigned for card 0, bit\\[3:2\\] are assigned for card 1. Card 0 maps and internally routes clock divider\\[0:3\\] outputs to cclk_out\\[1:0\\] pins, depending on bit value. 00 : Clock divider 0; 01 : Clock divider 1; 10 : Clock divider 2; 11 : Clock divider 3."]
8pub type CLKSRC_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
9impl R {
10    #[doc = "Bits 0:3 - Clock divider source for two SD cards is supported. Each card has two bits assigned to it. For example, bit\\[1:0\\] are assigned for card 0, bit\\[3:2\\] are assigned for card 1. Card 0 maps and internally routes clock divider\\[0:3\\] outputs to cclk_out\\[1:0\\] pins, depending on bit value. 00 : Clock divider 0; 01 : Clock divider 1; 10 : Clock divider 2; 11 : Clock divider 3."]
11    #[inline(always)]
12    pub fn clksrc(&self) -> CLKSRC_R {
13        CLKSRC_R::new((self.bits & 0x0f) as u8)
14    }
15}
16#[cfg(feature = "impl-register-debug")]
17impl core::fmt::Debug for R {
18    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
19        f.debug_struct("CLKSRC")
20            .field("clksrc", &self.clksrc())
21            .finish()
22    }
23}
24impl W {
25    #[doc = "Bits 0:3 - Clock divider source for two SD cards is supported. Each card has two bits assigned to it. For example, bit\\[1:0\\] are assigned for card 0, bit\\[3:2\\] are assigned for card 1. Card 0 maps and internally routes clock divider\\[0:3\\] outputs to cclk_out\\[1:0\\] pins, depending on bit value. 00 : Clock divider 0; 01 : Clock divider 1; 10 : Clock divider 2; 11 : Clock divider 3."]
26    #[inline(always)]
27    pub fn clksrc(&mut self) -> CLKSRC_W<CLKSRC_SPEC> {
28        CLKSRC_W::new(self, 0)
29    }
30}
31#[doc = "Clock source selection register\n\nYou can [`read`](crate::Reg::read) this register and get [`clksrc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clksrc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
32pub struct CLKSRC_SPEC;
33impl crate::RegisterSpec for CLKSRC_SPEC {
34    type Ux = u32;
35}
36#[doc = "`read()` method returns [`clksrc::R`](R) reader structure"]
37impl crate::Readable for CLKSRC_SPEC {}
38#[doc = "`write(|w| ..)` method takes [`clksrc::W`](W) writer structure"]
39impl crate::Writable for CLKSRC_SPEC {
40    type Safety = crate::Unsafe;
41}
42#[doc = "`reset()` method sets CLKSRC to value 0"]
43impl crate::Resettable for CLKSRC_SPEC {}
esp32/sdhost/clksrc.rs

esp32/sdhost/
clksrc.rs
