esp32/mcpwm0/
cap_timer_cfg.rs

1#[doc = "Register `CAP_TIMER_CFG` reader"]
2pub type R = crate::R<CAP_TIMER_CFG_SPEC>;
3#[doc = "Register `CAP_TIMER_CFG` writer"]
4pub type W = crate::W<CAP_TIMER_CFG_SPEC>;
5#[doc = "Field `CAP_TIMER_EN` reader - "]
6pub type CAP_TIMER_EN_R = crate::BitReader;
7#[doc = "Field `CAP_TIMER_EN` writer - "]
8pub type CAP_TIMER_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `CAP_SYNCI_EN` reader - "]
10pub type CAP_SYNCI_EN_R = crate::BitReader;
11#[doc = "Field `CAP_SYNCI_EN` writer - "]
12pub type CAP_SYNCI_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `CAP_SYNCI_SEL` reader - "]
14pub type CAP_SYNCI_SEL_R = crate::FieldReader;
15#[doc = "Field `CAP_SYNCI_SEL` writer - "]
16pub type CAP_SYNCI_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
17#[doc = "Field `CAP_SYNC_SW` writer - "]
18pub type CAP_SYNC_SW_W<'a, REG> = crate::BitWriter<'a, REG>;
19impl R {
20    #[doc = "Bit 0"]
21    #[inline(always)]
22    pub fn cap_timer_en(&self) -> CAP_TIMER_EN_R {
23        CAP_TIMER_EN_R::new((self.bits & 1) != 0)
24    }
25    #[doc = "Bit 1"]
26    #[inline(always)]
27    pub fn cap_synci_en(&self) -> CAP_SYNCI_EN_R {
28        CAP_SYNCI_EN_R::new(((self.bits >> 1) & 1) != 0)
29    }
30    #[doc = "Bits 2:4"]
31    #[inline(always)]
32    pub fn cap_synci_sel(&self) -> CAP_SYNCI_SEL_R {
33        CAP_SYNCI_SEL_R::new(((self.bits >> 2) & 7) as u8)
34    }
35}
36#[cfg(feature = "impl-register-debug")]
37impl core::fmt::Debug for R {
38    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
39        f.debug_struct("CAP_TIMER_CFG")
40            .field("cap_timer_en", &self.cap_timer_en())
41            .field("cap_synci_en", &self.cap_synci_en())
42            .field("cap_synci_sel", &self.cap_synci_sel())
43            .finish()
44    }
45}
46impl W {
47    #[doc = "Bit 0"]
48    #[inline(always)]
49    pub fn cap_timer_en(&mut self) -> CAP_TIMER_EN_W<CAP_TIMER_CFG_SPEC> {
50        CAP_TIMER_EN_W::new(self, 0)
51    }
52    #[doc = "Bit 1"]
53    #[inline(always)]
54    pub fn cap_synci_en(&mut self) -> CAP_SYNCI_EN_W<CAP_TIMER_CFG_SPEC> {
55        CAP_SYNCI_EN_W::new(self, 1)
56    }
57    #[doc = "Bits 2:4"]
58    #[inline(always)]
59    pub fn cap_synci_sel(&mut self) -> CAP_SYNCI_SEL_W<CAP_TIMER_CFG_SPEC> {
60        CAP_SYNCI_SEL_W::new(self, 2)
61    }
62    #[doc = "Bit 5"]
63    #[inline(always)]
64    pub fn cap_sync_sw(&mut self) -> CAP_SYNC_SW_W<CAP_TIMER_CFG_SPEC> {
65        CAP_SYNC_SW_W::new(self, 5)
66    }
67}
68#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`cap_timer_cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cap_timer_cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
69pub struct CAP_TIMER_CFG_SPEC;
70impl crate::RegisterSpec for CAP_TIMER_CFG_SPEC {
71    type Ux = u32;
72}
73#[doc = "`read()` method returns [`cap_timer_cfg::R`](R) reader structure"]
74impl crate::Readable for CAP_TIMER_CFG_SPEC {}
75#[doc = "`write(|w| ..)` method takes [`cap_timer_cfg::W`](W) writer structure"]
76impl crate::Writable for CAP_TIMER_CFG_SPEC {
77    type Safety = crate::Unsafe;
78}
79#[doc = "`reset()` method sets CAP_TIMER_CFG to value 0"]
80impl crate::Resettable for CAP_TIMER_CFG_SPEC {}
esp32/mcpwm0/cap_timer_cfg.rs

esp32/mcpwm0/
cap_timer_cfg.rs
