1#[doc = "Register `INT_ENA` reader"]
2pub type R = crate::R<INT_ENA_SPEC>;
3#[doc = "Register `INT_ENA` writer"]
4pub type W = crate::W<INT_ENA_SPEC>;
5#[doc = "Field `RXFIFO_FULL` reader - The enable bit for rxfifo_full_int interrupt."]
6pub type RXFIFO_FULL_R = crate::BitReader;
7#[doc = "Field `RXFIFO_FULL` writer - The enable bit for rxfifo_full_int interrupt."]
8pub type RXFIFO_FULL_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `TXFIFO_EMPTY` reader - The enable bit for txfifo_empty_int interrupt."]
10pub type TXFIFO_EMPTY_R = crate::BitReader;
11#[doc = "Field `TXFIFO_EMPTY` writer - The enable bit for txfifo_empty_int interrupt."]
12pub type TXFIFO_EMPTY_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `RXFIFO_OVF` reader - The enable bit for rxfifo_ovf_int interrupt."]
14pub type RXFIFO_OVF_R = crate::BitReader;
15#[doc = "Field `RXFIFO_OVF` writer - The enable bit for rxfifo_ovf_int interrupt."]
16pub type RXFIFO_OVF_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `END_DETECT` reader - The enable bit for end_detect_int interrupt."]
18pub type END_DETECT_R = crate::BitReader;
19#[doc = "Field `END_DETECT` writer - The enable bit for end_detect_int interrupt."]
20pub type END_DETECT_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `SLAVE_TRAN_COMP` reader - The enable bit for slave_tran_comp_int interrupt."]
22pub type SLAVE_TRAN_COMP_R = crate::BitReader;
23#[doc = "Field `SLAVE_TRAN_COMP` writer - The enable bit for slave_tran_comp_int interrupt."]
24pub type SLAVE_TRAN_COMP_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `ARBITRATION_LOST` reader - The enable bit for arbitration_lost_int interrupt."]
26pub type ARBITRATION_LOST_R = crate::BitReader;
27#[doc = "Field `ARBITRATION_LOST` writer - The enable bit for arbitration_lost_int interrupt."]
28pub type ARBITRATION_LOST_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `MASTER_TRAN_COMP` reader - The enable bit for master_tran_comp_int interrupt."]
30pub type MASTER_TRAN_COMP_R = crate::BitReader;
31#[doc = "Field `MASTER_TRAN_COMP` writer - The enable bit for master_tran_comp_int interrupt."]
32pub type MASTER_TRAN_COMP_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `TRANS_COMPLETE` reader - The enable bit for trans_complete_int interrupt."]
34pub type TRANS_COMPLETE_R = crate::BitReader;
35#[doc = "Field `TRANS_COMPLETE` writer - The enable bit for trans_complete_int interrupt."]
36pub type TRANS_COMPLETE_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `TIME_OUT` reader - The enable bit for time_out_int interrupt."]
38pub type TIME_OUT_R = crate::BitReader;
39#[doc = "Field `TIME_OUT` writer - The enable bit for time_out_int interrupt."]
40pub type TIME_OUT_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `TRANS_START` reader - The enable bit for trans_start_int interrupt."]
42pub type TRANS_START_R = crate::BitReader;
43#[doc = "Field `TRANS_START` writer - The enable bit for trans_start_int interrupt."]
44pub type TRANS_START_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `NACK` reader - The enable bit for ack_err_int interrupt."]
46pub type NACK_R = crate::BitReader;
47#[doc = "Field `NACK` writer - The enable bit for ack_err_int interrupt."]
48pub type NACK_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `RX_REC_FULL` reader - The enable bit for rx_rec_full_int interrupt."]
50pub type RX_REC_FULL_R = crate::BitReader;
51#[doc = "Field `RX_REC_FULL` writer - The enable bit for rx_rec_full_int interrupt."]
52pub type RX_REC_FULL_W<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `TX_SEND_EMPTY` reader - The enable bit for tx_send_empty_int interrupt."]
54pub type TX_SEND_EMPTY_R = crate::BitReader;
55#[doc = "Field `TX_SEND_EMPTY` writer - The enable bit for tx_send_empty_int interrupt."]
56pub type TX_SEND_EMPTY_W<'a, REG> = crate::BitWriter<'a, REG>;
57impl R {
58 #[doc = "Bit 0 - The enable bit for rxfifo_full_int interrupt."]
59 #[inline(always)]
60 pub fn rxfifo_full(&self) -> RXFIFO_FULL_R {
61 RXFIFO_FULL_R::new((self.bits & 1) != 0)
62 }
63 #[doc = "Bit 1 - The enable bit for txfifo_empty_int interrupt."]
64 #[inline(always)]
65 pub fn txfifo_empty(&self) -> TXFIFO_EMPTY_R {
66 TXFIFO_EMPTY_R::new(((self.bits >> 1) & 1) != 0)
67 }
68 #[doc = "Bit 2 - The enable bit for rxfifo_ovf_int interrupt."]
69 #[inline(always)]
70 pub fn rxfifo_ovf(&self) -> RXFIFO_OVF_R {
71 RXFIFO_OVF_R::new(((self.bits >> 2) & 1) != 0)
72 }
73 #[doc = "Bit 3 - The enable bit for end_detect_int interrupt."]
74 #[inline(always)]
75 pub fn end_detect(&self) -> END_DETECT_R {
76 END_DETECT_R::new(((self.bits >> 3) & 1) != 0)
77 }
78 #[doc = "Bit 4 - The enable bit for slave_tran_comp_int interrupt."]
79 #[inline(always)]
80 pub fn slave_tran_comp(&self) -> SLAVE_TRAN_COMP_R {
81 SLAVE_TRAN_COMP_R::new(((self.bits >> 4) & 1) != 0)
82 }
83 #[doc = "Bit 5 - The enable bit for arbitration_lost_int interrupt."]
84 #[inline(always)]
85 pub fn arbitration_lost(&self) -> ARBITRATION_LOST_R {
86 ARBITRATION_LOST_R::new(((self.bits >> 5) & 1) != 0)
87 }
88 #[doc = "Bit 6 - The enable bit for master_tran_comp_int interrupt."]
89 #[inline(always)]
90 pub fn master_tran_comp(&self) -> MASTER_TRAN_COMP_R {
91 MASTER_TRAN_COMP_R::new(((self.bits >> 6) & 1) != 0)
92 }
93 #[doc = "Bit 7 - The enable bit for trans_complete_int interrupt."]
94 #[inline(always)]
95 pub fn trans_complete(&self) -> TRANS_COMPLETE_R {
96 TRANS_COMPLETE_R::new(((self.bits >> 7) & 1) != 0)
97 }
98 #[doc = "Bit 8 - The enable bit for time_out_int interrupt."]
99 #[inline(always)]
100 pub fn time_out(&self) -> TIME_OUT_R {
101 TIME_OUT_R::new(((self.bits >> 8) & 1) != 0)
102 }
103 #[doc = "Bit 9 - The enable bit for trans_start_int interrupt."]
104 #[inline(always)]
105 pub fn trans_start(&self) -> TRANS_START_R {
106 TRANS_START_R::new(((self.bits >> 9) & 1) != 0)
107 }
108 #[doc = "Bit 10 - The enable bit for ack_err_int interrupt."]
109 #[inline(always)]
110 pub fn nack(&self) -> NACK_R {
111 NACK_R::new(((self.bits >> 10) & 1) != 0)
112 }
113 #[doc = "Bit 11 - The enable bit for rx_rec_full_int interrupt."]
114 #[inline(always)]
115 pub fn rx_rec_full(&self) -> RX_REC_FULL_R {
116 RX_REC_FULL_R::new(((self.bits >> 11) & 1) != 0)
117 }
118 #[doc = "Bit 12 - The enable bit for tx_send_empty_int interrupt."]
119 #[inline(always)]
120 pub fn tx_send_empty(&self) -> TX_SEND_EMPTY_R {
121 TX_SEND_EMPTY_R::new(((self.bits >> 12) & 1) != 0)
122 }
123}
124#[cfg(feature = "impl-register-debug")]
125impl core::fmt::Debug for R {
126 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
127 f.debug_struct("INT_ENA")
128 .field("rxfifo_full", &self.rxfifo_full())
129 .field("txfifo_empty", &self.txfifo_empty())
130 .field("rxfifo_ovf", &self.rxfifo_ovf())
131 .field("end_detect", &self.end_detect())
132 .field("slave_tran_comp", &self.slave_tran_comp())
133 .field("arbitration_lost", &self.arbitration_lost())
134 .field("master_tran_comp", &self.master_tran_comp())
135 .field("trans_complete", &self.trans_complete())
136 .field("time_out", &self.time_out())
137 .field("trans_start", &self.trans_start())
138 .field("nack", &self.nack())
139 .field("rx_rec_full", &self.rx_rec_full())
140 .field("tx_send_empty", &self.tx_send_empty())
141 .finish()
142 }
143}
144impl W {
145 #[doc = "Bit 0 - The enable bit for rxfifo_full_int interrupt."]
146 #[inline(always)]
147 pub fn rxfifo_full(&mut self) -> RXFIFO_FULL_W<INT_ENA_SPEC> {
148 RXFIFO_FULL_W::new(self, 0)
149 }
150 #[doc = "Bit 1 - The enable bit for txfifo_empty_int interrupt."]
151 #[inline(always)]
152 pub fn txfifo_empty(&mut self) -> TXFIFO_EMPTY_W<INT_ENA_SPEC> {
153 TXFIFO_EMPTY_W::new(self, 1)
154 }
155 #[doc = "Bit 2 - The enable bit for rxfifo_ovf_int interrupt."]
156 #[inline(always)]
157 pub fn rxfifo_ovf(&mut self) -> RXFIFO_OVF_W<INT_ENA_SPEC> {
158 RXFIFO_OVF_W::new(self, 2)
159 }
160 #[doc = "Bit 3 - The enable bit for end_detect_int interrupt."]
161 #[inline(always)]
162 pub fn end_detect(&mut self) -> END_DETECT_W<INT_ENA_SPEC> {
163 END_DETECT_W::new(self, 3)
164 }
165 #[doc = "Bit 4 - The enable bit for slave_tran_comp_int interrupt."]
166 #[inline(always)]
167 pub fn slave_tran_comp(&mut self) -> SLAVE_TRAN_COMP_W<INT_ENA_SPEC> {
168 SLAVE_TRAN_COMP_W::new(self, 4)
169 }
170 #[doc = "Bit 5 - The enable bit for arbitration_lost_int interrupt."]
171 #[inline(always)]
172 pub fn arbitration_lost(&mut self) -> ARBITRATION_LOST_W<INT_ENA_SPEC> {
173 ARBITRATION_LOST_W::new(self, 5)
174 }
175 #[doc = "Bit 6 - The enable bit for master_tran_comp_int interrupt."]
176 #[inline(always)]
177 pub fn master_tran_comp(&mut self) -> MASTER_TRAN_COMP_W<INT_ENA_SPEC> {
178 MASTER_TRAN_COMP_W::new(self, 6)
179 }
180 #[doc = "Bit 7 - The enable bit for trans_complete_int interrupt."]
181 #[inline(always)]
182 pub fn trans_complete(&mut self) -> TRANS_COMPLETE_W<INT_ENA_SPEC> {
183 TRANS_COMPLETE_W::new(self, 7)
184 }
185 #[doc = "Bit 8 - The enable bit for time_out_int interrupt."]
186 #[inline(always)]
187 pub fn time_out(&mut self) -> TIME_OUT_W<INT_ENA_SPEC> {
188 TIME_OUT_W::new(self, 8)
189 }
190 #[doc = "Bit 9 - The enable bit for trans_start_int interrupt."]
191 #[inline(always)]
192 pub fn trans_start(&mut self) -> TRANS_START_W<INT_ENA_SPEC> {
193 TRANS_START_W::new(self, 9)
194 }
195 #[doc = "Bit 10 - The enable bit for ack_err_int interrupt."]
196 #[inline(always)]
197 pub fn nack(&mut self) -> NACK_W<INT_ENA_SPEC> {
198 NACK_W::new(self, 10)
199 }
200 #[doc = "Bit 11 - The enable bit for rx_rec_full_int interrupt."]
201 #[inline(always)]
202 pub fn rx_rec_full(&mut self) -> RX_REC_FULL_W<INT_ENA_SPEC> {
203 RX_REC_FULL_W::new(self, 11)
204 }
205 #[doc = "Bit 12 - The enable bit for tx_send_empty_int interrupt."]
206 #[inline(always)]
207 pub fn tx_send_empty(&mut self) -> TX_SEND_EMPTY_W<INT_ENA_SPEC> {
208 TX_SEND_EMPTY_W::new(self, 12)
209 }
210}
211#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
212pub struct INT_ENA_SPEC;
213impl crate::RegisterSpec for INT_ENA_SPEC {
214 type Ux = u32;
215}
216#[doc = "`read()` method returns [`int_ena::R`](R) reader structure"]
217impl crate::Readable for INT_ENA_SPEC {}
218#[doc = "`write(|w| ..)` method takes [`int_ena::W`](W) writer structure"]
219impl crate::Writable for INT_ENA_SPEC {
220 type Safety = crate::Unsafe;
221}
222#[doc = "`reset()` method sets INT_ENA to value 0"]
223impl crate::Resettable for INT_ENA_SPEC {}