esp32/efuse/
blk0_wdata5.rs

1#[doc = "Register `BLK0_WDATA5` reader"]
2pub type R = crate::R<BLK0_WDATA5_SPEC>;
3#[doc = "Register `BLK0_WDATA5` writer"]
4pub type W = crate::W<BLK0_WDATA5_SPEC>;
5#[doc = "Field `SPI_PAD_CONFIG_CLK` reader - "]
6pub type SPI_PAD_CONFIG_CLK_R = crate::FieldReader;
7#[doc = "Field `SPI_PAD_CONFIG_Q` reader - "]
8pub type SPI_PAD_CONFIG_Q_R = crate::FieldReader;
9#[doc = "Field `SPI_PAD_CONFIG_D` reader - "]
10pub type SPI_PAD_CONFIG_D_R = crate::FieldReader;
11#[doc = "Field `SPI_PAD_CONFIG_CS0` reader - "]
12pub type SPI_PAD_CONFIG_CS0_R = crate::FieldReader;
13#[doc = "Field `CHIP_VER_REV2` reader - "]
14pub type CHIP_VER_REV2_R = crate::BitReader;
15#[doc = "Field `RESERVE_0_181` reader - "]
16pub type RESERVE_0_181_R = crate::BitReader;
17#[doc = "Field `RESERVE_0_181` writer - "]
18pub type RESERVE_0_181_W<'a, REG> = crate::BitWriter<'a, REG>;
19#[doc = "Field `VOL_LEVEL_HP_INV` reader - "]
20pub type VOL_LEVEL_HP_INV_R = crate::FieldReader;
21#[doc = "Field `WAFER_VERSION_MINOR` reader - "]
22pub type WAFER_VERSION_MINOR_R = crate::FieldReader;
23#[doc = "Field `RESERVE_0_186` reader - "]
24pub type RESERVE_0_186_R = crate::FieldReader;
25#[doc = "Field `RESERVE_0_186` writer - "]
26pub type RESERVE_0_186_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
27#[doc = "Field `FLASH_CRYPT_CONFIG` reader - "]
28pub type FLASH_CRYPT_CONFIG_R = crate::FieldReader;
29impl R {
30    #[doc = "Bits 0:4"]
31    #[inline(always)]
32    pub fn spi_pad_config_clk(&self) -> SPI_PAD_CONFIG_CLK_R {
33        SPI_PAD_CONFIG_CLK_R::new((self.bits & 0x1f) as u8)
34    }
35    #[doc = "Bits 5:9"]
36    #[inline(always)]
37    pub fn spi_pad_config_q(&self) -> SPI_PAD_CONFIG_Q_R {
38        SPI_PAD_CONFIG_Q_R::new(((self.bits >> 5) & 0x1f) as u8)
39    }
40    #[doc = "Bits 10:14"]
41    #[inline(always)]
42    pub fn spi_pad_config_d(&self) -> SPI_PAD_CONFIG_D_R {
43        SPI_PAD_CONFIG_D_R::new(((self.bits >> 10) & 0x1f) as u8)
44    }
45    #[doc = "Bits 15:19"]
46    #[inline(always)]
47    pub fn spi_pad_config_cs0(&self) -> SPI_PAD_CONFIG_CS0_R {
48        SPI_PAD_CONFIG_CS0_R::new(((self.bits >> 15) & 0x1f) as u8)
49    }
50    #[doc = "Bit 20"]
51    #[inline(always)]
52    pub fn chip_ver_rev2(&self) -> CHIP_VER_REV2_R {
53        CHIP_VER_REV2_R::new(((self.bits >> 20) & 1) != 0)
54    }
55    #[doc = "Bit 21"]
56    #[inline(always)]
57    pub fn reserve_0_181(&self) -> RESERVE_0_181_R {
58        RESERVE_0_181_R::new(((self.bits >> 21) & 1) != 0)
59    }
60    #[doc = "Bits 22:23"]
61    #[inline(always)]
62    pub fn vol_level_hp_inv(&self) -> VOL_LEVEL_HP_INV_R {
63        VOL_LEVEL_HP_INV_R::new(((self.bits >> 22) & 3) as u8)
64    }
65    #[doc = "Bits 24:25"]
66    #[inline(always)]
67    pub fn wafer_version_minor(&self) -> WAFER_VERSION_MINOR_R {
68        WAFER_VERSION_MINOR_R::new(((self.bits >> 24) & 3) as u8)
69    }
70    #[doc = "Bits 26:27"]
71    #[inline(always)]
72    pub fn reserve_0_186(&self) -> RESERVE_0_186_R {
73        RESERVE_0_186_R::new(((self.bits >> 26) & 3) as u8)
74    }
75    #[doc = "Bits 28:31"]
76    #[inline(always)]
77    pub fn flash_crypt_config(&self) -> FLASH_CRYPT_CONFIG_R {
78        FLASH_CRYPT_CONFIG_R::new(((self.bits >> 28) & 0x0f) as u8)
79    }
80}
81#[cfg(feature = "impl-register-debug")]
82impl core::fmt::Debug for R {
83    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
84        f.debug_struct("BLK0_WDATA5")
85            .field("spi_pad_config_clk", &self.spi_pad_config_clk())
86            .field("spi_pad_config_q", &self.spi_pad_config_q())
87            .field("spi_pad_config_d", &self.spi_pad_config_d())
88            .field("spi_pad_config_cs0", &self.spi_pad_config_cs0())
89            .field("chip_ver_rev2", &self.chip_ver_rev2())
90            .field("reserve_0_181", &self.reserve_0_181())
91            .field("vol_level_hp_inv", &self.vol_level_hp_inv())
92            .field("wafer_version_minor", &self.wafer_version_minor())
93            .field("reserve_0_186", &self.reserve_0_186())
94            .field("flash_crypt_config", &self.flash_crypt_config())
95            .finish()
96    }
97}
98impl W {
99    #[doc = "Bit 21"]
100    #[inline(always)]
101    pub fn reserve_0_181(&mut self) -> RESERVE_0_181_W<BLK0_WDATA5_SPEC> {
102        RESERVE_0_181_W::new(self, 21)
103    }
104    #[doc = "Bits 26:27"]
105    #[inline(always)]
106    pub fn reserve_0_186(&mut self) -> RESERVE_0_186_W<BLK0_WDATA5_SPEC> {
107        RESERVE_0_186_W::new(self, 26)
108    }
109}
110#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`blk0_wdata5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`blk0_wdata5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
111pub struct BLK0_WDATA5_SPEC;
112impl crate::RegisterSpec for BLK0_WDATA5_SPEC {
113    type Ux = u32;
114}
115#[doc = "`read()` method returns [`blk0_wdata5::R`](R) reader structure"]
116impl crate::Readable for BLK0_WDATA5_SPEC {}
117#[doc = "`write(|w| ..)` method takes [`blk0_wdata5::W`](W) writer structure"]
118impl crate::Writable for BLK0_WDATA5_SPEC {
119    type Safety = crate::Unsafe;
120}
121#[doc = "`reset()` method sets BLK0_WDATA5 to value 0"]
122impl crate::Resettable for BLK0_WDATA5_SPEC {}
esp32/efuse/blk0_wdata5.rs

esp32/efuse/
blk0_wdata5.rs
