esp32/dport/
pro_cache_ctrl.rs

1#[doc = "Register `PRO_CACHE_CTRL` reader"]
2pub type R = crate::R<PRO_CACHE_CTRL_SPEC>;
3#[doc = "Register `PRO_CACHE_CTRL` writer"]
4pub type W = crate::W<PRO_CACHE_CTRL_SPEC>;
5#[doc = "Field `PRO_CACHE_MODE` reader - "]
6pub type PRO_CACHE_MODE_R = crate::BitReader;
7#[doc = "Field `PRO_CACHE_MODE` writer - "]
8pub type PRO_CACHE_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `PRO_CACHE_ENABLE` reader - "]
10pub type PRO_CACHE_ENABLE_R = crate::BitReader;
11#[doc = "Field `PRO_CACHE_ENABLE` writer - "]
12pub type PRO_CACHE_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `PRO_CACHE_FLUSH_ENA` reader - "]
14pub type PRO_CACHE_FLUSH_ENA_R = crate::BitReader;
15#[doc = "Field `PRO_CACHE_FLUSH_ENA` writer - "]
16pub type PRO_CACHE_FLUSH_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `PRO_CACHE_FLUSH_DONE` reader - "]
18pub type PRO_CACHE_FLUSH_DONE_R = crate::BitReader;
19#[doc = "Field `PRO_CACHE_LOCK_0_EN` reader - "]
20pub type PRO_CACHE_LOCK_0_EN_R = crate::BitReader;
21#[doc = "Field `PRO_CACHE_LOCK_0_EN` writer - "]
22pub type PRO_CACHE_LOCK_0_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
23#[doc = "Field `PRO_CACHE_LOCK_1_EN` reader - "]
24pub type PRO_CACHE_LOCK_1_EN_R = crate::BitReader;
25#[doc = "Field `PRO_CACHE_LOCK_1_EN` writer - "]
26pub type PRO_CACHE_LOCK_1_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
27#[doc = "Field `PRO_CACHE_LOCK_2_EN` reader - "]
28pub type PRO_CACHE_LOCK_2_EN_R = crate::BitReader;
29#[doc = "Field `PRO_CACHE_LOCK_2_EN` writer - "]
30pub type PRO_CACHE_LOCK_2_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
31#[doc = "Field `PRO_CACHE_LOCK_3_EN` reader - "]
32pub type PRO_CACHE_LOCK_3_EN_R = crate::BitReader;
33#[doc = "Field `PRO_CACHE_LOCK_3_EN` writer - "]
34pub type PRO_CACHE_LOCK_3_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
35#[doc = "Field `PRO_SINGLE_IRAM_ENA` reader - "]
36pub type PRO_SINGLE_IRAM_ENA_R = crate::BitReader;
37#[doc = "Field `PRO_SINGLE_IRAM_ENA` writer - "]
38pub type PRO_SINGLE_IRAM_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
39#[doc = "Field `PRO_DRAM_SPLIT` reader - "]
40pub type PRO_DRAM_SPLIT_R = crate::BitReader;
41#[doc = "Field `PRO_DRAM_SPLIT` writer - "]
42pub type PRO_DRAM_SPLIT_W<'a, REG> = crate::BitWriter<'a, REG>;
43#[doc = "Field `PRO_AHB_SPI_REQ` reader - "]
44pub type PRO_AHB_SPI_REQ_R = crate::BitReader;
45#[doc = "Field `PRO_SLAVE_REQ` reader - "]
46pub type PRO_SLAVE_REQ_R = crate::BitReader;
47#[doc = "Field `AHB_SPI_REQ` reader - "]
48pub type AHB_SPI_REQ_R = crate::BitReader;
49#[doc = "Field `SLAVE_REQ` reader - "]
50pub type SLAVE_REQ_R = crate::BitReader;
51#[doc = "Field `PRO_DRAM_HL` reader - "]
52pub type PRO_DRAM_HL_R = crate::BitReader;
53#[doc = "Field `PRO_DRAM_HL` writer - "]
54pub type PRO_DRAM_HL_W<'a, REG> = crate::BitWriter<'a, REG>;
55impl R {
56    #[doc = "Bit 2"]
57    #[inline(always)]
58    pub fn pro_cache_mode(&self) -> PRO_CACHE_MODE_R {
59        PRO_CACHE_MODE_R::new(((self.bits >> 2) & 1) != 0)
60    }
61    #[doc = "Bit 3"]
62    #[inline(always)]
63    pub fn pro_cache_enable(&self) -> PRO_CACHE_ENABLE_R {
64        PRO_CACHE_ENABLE_R::new(((self.bits >> 3) & 1) != 0)
65    }
66    #[doc = "Bit 4"]
67    #[inline(always)]
68    pub fn pro_cache_flush_ena(&self) -> PRO_CACHE_FLUSH_ENA_R {
69        PRO_CACHE_FLUSH_ENA_R::new(((self.bits >> 4) & 1) != 0)
70    }
71    #[doc = "Bit 5"]
72    #[inline(always)]
73    pub fn pro_cache_flush_done(&self) -> PRO_CACHE_FLUSH_DONE_R {
74        PRO_CACHE_FLUSH_DONE_R::new(((self.bits >> 5) & 1) != 0)
75    }
76    #[doc = "Bit 6"]
77    #[inline(always)]
78    pub fn pro_cache_lock_0_en(&self) -> PRO_CACHE_LOCK_0_EN_R {
79        PRO_CACHE_LOCK_0_EN_R::new(((self.bits >> 6) & 1) != 0)
80    }
81    #[doc = "Bit 7"]
82    #[inline(always)]
83    pub fn pro_cache_lock_1_en(&self) -> PRO_CACHE_LOCK_1_EN_R {
84        PRO_CACHE_LOCK_1_EN_R::new(((self.bits >> 7) & 1) != 0)
85    }
86    #[doc = "Bit 8"]
87    #[inline(always)]
88    pub fn pro_cache_lock_2_en(&self) -> PRO_CACHE_LOCK_2_EN_R {
89        PRO_CACHE_LOCK_2_EN_R::new(((self.bits >> 8) & 1) != 0)
90    }
91    #[doc = "Bit 9"]
92    #[inline(always)]
93    pub fn pro_cache_lock_3_en(&self) -> PRO_CACHE_LOCK_3_EN_R {
94        PRO_CACHE_LOCK_3_EN_R::new(((self.bits >> 9) & 1) != 0)
95    }
96    #[doc = "Bit 10"]
97    #[inline(always)]
98    pub fn pro_single_iram_ena(&self) -> PRO_SINGLE_IRAM_ENA_R {
99        PRO_SINGLE_IRAM_ENA_R::new(((self.bits >> 10) & 1) != 0)
100    }
101    #[doc = "Bit 11"]
102    #[inline(always)]
103    pub fn pro_dram_split(&self) -> PRO_DRAM_SPLIT_R {
104        PRO_DRAM_SPLIT_R::new(((self.bits >> 11) & 1) != 0)
105    }
106    #[doc = "Bit 12"]
107    #[inline(always)]
108    pub fn pro_ahb_spi_req(&self) -> PRO_AHB_SPI_REQ_R {
109        PRO_AHB_SPI_REQ_R::new(((self.bits >> 12) & 1) != 0)
110    }
111    #[doc = "Bit 13"]
112    #[inline(always)]
113    pub fn pro_slave_req(&self) -> PRO_SLAVE_REQ_R {
114        PRO_SLAVE_REQ_R::new(((self.bits >> 13) & 1) != 0)
115    }
116    #[doc = "Bit 14"]
117    #[inline(always)]
118    pub fn ahb_spi_req(&self) -> AHB_SPI_REQ_R {
119        AHB_SPI_REQ_R::new(((self.bits >> 14) & 1) != 0)
120    }
121    #[doc = "Bit 15"]
122    #[inline(always)]
123    pub fn slave_req(&self) -> SLAVE_REQ_R {
124        SLAVE_REQ_R::new(((self.bits >> 15) & 1) != 0)
125    }
126    #[doc = "Bit 16"]
127    #[inline(always)]
128    pub fn pro_dram_hl(&self) -> PRO_DRAM_HL_R {
129        PRO_DRAM_HL_R::new(((self.bits >> 16) & 1) != 0)
130    }
131}
132#[cfg(feature = "impl-register-debug")]
133impl core::fmt::Debug for R {
134    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
135        f.debug_struct("PRO_CACHE_CTRL")
136            .field("pro_cache_mode", &self.pro_cache_mode())
137            .field("pro_cache_enable", &self.pro_cache_enable())
138            .field("pro_cache_flush_ena", &self.pro_cache_flush_ena())
139            .field("pro_cache_flush_done", &self.pro_cache_flush_done())
140            .field("pro_cache_lock_0_en", &self.pro_cache_lock_0_en())
141            .field("pro_cache_lock_1_en", &self.pro_cache_lock_1_en())
142            .field("pro_cache_lock_2_en", &self.pro_cache_lock_2_en())
143            .field("pro_cache_lock_3_en", &self.pro_cache_lock_3_en())
144            .field("pro_single_iram_ena", &self.pro_single_iram_ena())
145            .field("pro_dram_split", &self.pro_dram_split())
146            .field("pro_ahb_spi_req", &self.pro_ahb_spi_req())
147            .field("pro_slave_req", &self.pro_slave_req())
148            .field("ahb_spi_req", &self.ahb_spi_req())
149            .field("slave_req", &self.slave_req())
150            .field("pro_dram_hl", &self.pro_dram_hl())
151            .finish()
152    }
153}
154impl W {
155    #[doc = "Bit 2"]
156    #[inline(always)]
157    pub fn pro_cache_mode(&mut self) -> PRO_CACHE_MODE_W<PRO_CACHE_CTRL_SPEC> {
158        PRO_CACHE_MODE_W::new(self, 2)
159    }
160    #[doc = "Bit 3"]
161    #[inline(always)]
162    pub fn pro_cache_enable(&mut self) -> PRO_CACHE_ENABLE_W<PRO_CACHE_CTRL_SPEC> {
163        PRO_CACHE_ENABLE_W::new(self, 3)
164    }
165    #[doc = "Bit 4"]
166    #[inline(always)]
167    pub fn pro_cache_flush_ena(&mut self) -> PRO_CACHE_FLUSH_ENA_W<PRO_CACHE_CTRL_SPEC> {
168        PRO_CACHE_FLUSH_ENA_W::new(self, 4)
169    }
170    #[doc = "Bit 6"]
171    #[inline(always)]
172    pub fn pro_cache_lock_0_en(&mut self) -> PRO_CACHE_LOCK_0_EN_W<PRO_CACHE_CTRL_SPEC> {
173        PRO_CACHE_LOCK_0_EN_W::new(self, 6)
174    }
175    #[doc = "Bit 7"]
176    #[inline(always)]
177    pub fn pro_cache_lock_1_en(&mut self) -> PRO_CACHE_LOCK_1_EN_W<PRO_CACHE_CTRL_SPEC> {
178        PRO_CACHE_LOCK_1_EN_W::new(self, 7)
179    }
180    #[doc = "Bit 8"]
181    #[inline(always)]
182    pub fn pro_cache_lock_2_en(&mut self) -> PRO_CACHE_LOCK_2_EN_W<PRO_CACHE_CTRL_SPEC> {
183        PRO_CACHE_LOCK_2_EN_W::new(self, 8)
184    }
185    #[doc = "Bit 9"]
186    #[inline(always)]
187    pub fn pro_cache_lock_3_en(&mut self) -> PRO_CACHE_LOCK_3_EN_W<PRO_CACHE_CTRL_SPEC> {
188        PRO_CACHE_LOCK_3_EN_W::new(self, 9)
189    }
190    #[doc = "Bit 10"]
191    #[inline(always)]
192    pub fn pro_single_iram_ena(&mut self) -> PRO_SINGLE_IRAM_ENA_W<PRO_CACHE_CTRL_SPEC> {
193        PRO_SINGLE_IRAM_ENA_W::new(self, 10)
194    }
195    #[doc = "Bit 11"]
196    #[inline(always)]
197    pub fn pro_dram_split(&mut self) -> PRO_DRAM_SPLIT_W<PRO_CACHE_CTRL_SPEC> {
198        PRO_DRAM_SPLIT_W::new(self, 11)
199    }
200    #[doc = "Bit 16"]
201    #[inline(always)]
202    pub fn pro_dram_hl(&mut self) -> PRO_DRAM_HL_W<PRO_CACHE_CTRL_SPEC> {
203        PRO_DRAM_HL_W::new(self, 16)
204    }
205}
206#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`pro_cache_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pro_cache_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
207pub struct PRO_CACHE_CTRL_SPEC;
208impl crate::RegisterSpec for PRO_CACHE_CTRL_SPEC {
209    type Ux = u32;
210}
211#[doc = "`read()` method returns [`pro_cache_ctrl::R`](R) reader structure"]
212impl crate::Readable for PRO_CACHE_CTRL_SPEC {}
213#[doc = "`write(|w| ..)` method takes [`pro_cache_ctrl::W`](W) writer structure"]
214impl crate::Writable for PRO_CACHE_CTRL_SPEC {
215    type Safety = crate::Unsafe;
216}
217#[doc = "`reset()` method sets PRO_CACHE_CTRL to value 0x10"]
218impl crate::Resettable for PRO_CACHE_CTRL_SPEC {
219    const RESET_VALUE: u32 = 0x10;
220}
esp32/dport/pro_cache_ctrl.rs

esp32/dport/
pro_cache_ctrl.rs
