esp32/dport/
mem_access_dbug0.rs

1#[doc = "Register `MEM_ACCESS_DBUG0` reader"]
2pub type R = crate::R<MEM_ACCESS_DBUG0_SPEC>;
3#[doc = "Field `PRO_ROM_MPU_AD` reader - "]
4pub type PRO_ROM_MPU_AD_R = crate::BitReader;
5#[doc = "Field `PRO_ROM_IA` reader - "]
6pub type PRO_ROM_IA_R = crate::BitReader;
7#[doc = "Field `APP_ROM_MPU_AD` reader - "]
8pub type APP_ROM_MPU_AD_R = crate::BitReader;
9#[doc = "Field `APP_ROM_IA` reader - "]
10pub type APP_ROM_IA_R = crate::BitReader;
11#[doc = "Field `SHARE_ROM_MPU_AD` reader - "]
12pub type SHARE_ROM_MPU_AD_R = crate::FieldReader;
13#[doc = "Field `SHARE_ROM_IA` reader - "]
14pub type SHARE_ROM_IA_R = crate::FieldReader;
15#[doc = "Field `INTERNAL_SRAM_MMU_AD` reader - "]
16pub type INTERNAL_SRAM_MMU_AD_R = crate::FieldReader;
17#[doc = "Field `INTERNAL_SRAM_IA` reader - "]
18pub type INTERNAL_SRAM_IA_R = crate::FieldReader<u16>;
19#[doc = "Field `INTERNAL_SRAM_MMU_MULTI_HIT` reader - "]
20pub type INTERNAL_SRAM_MMU_MULTI_HIT_R = crate::FieldReader;
21impl R {
22    #[doc = "Bit 0"]
23    #[inline(always)]
24    pub fn pro_rom_mpu_ad(&self) -> PRO_ROM_MPU_AD_R {
25        PRO_ROM_MPU_AD_R::new((self.bits & 1) != 0)
26    }
27    #[doc = "Bit 1"]
28    #[inline(always)]
29    pub fn pro_rom_ia(&self) -> PRO_ROM_IA_R {
30        PRO_ROM_IA_R::new(((self.bits >> 1) & 1) != 0)
31    }
32    #[doc = "Bit 2"]
33    #[inline(always)]
34    pub fn app_rom_mpu_ad(&self) -> APP_ROM_MPU_AD_R {
35        APP_ROM_MPU_AD_R::new(((self.bits >> 2) & 1) != 0)
36    }
37    #[doc = "Bit 3"]
38    #[inline(always)]
39    pub fn app_rom_ia(&self) -> APP_ROM_IA_R {
40        APP_ROM_IA_R::new(((self.bits >> 3) & 1) != 0)
41    }
42    #[doc = "Bits 4:5"]
43    #[inline(always)]
44    pub fn share_rom_mpu_ad(&self) -> SHARE_ROM_MPU_AD_R {
45        SHARE_ROM_MPU_AD_R::new(((self.bits >> 4) & 3) as u8)
46    }
47    #[doc = "Bits 6:9"]
48    #[inline(always)]
49    pub fn share_rom_ia(&self) -> SHARE_ROM_IA_R {
50        SHARE_ROM_IA_R::new(((self.bits >> 6) & 0x0f) as u8)
51    }
52    #[doc = "Bits 10:13"]
53    #[inline(always)]
54    pub fn internal_sram_mmu_ad(&self) -> INTERNAL_SRAM_MMU_AD_R {
55        INTERNAL_SRAM_MMU_AD_R::new(((self.bits >> 10) & 0x0f) as u8)
56    }
57    #[doc = "Bits 14:25"]
58    #[inline(always)]
59    pub fn internal_sram_ia(&self) -> INTERNAL_SRAM_IA_R {
60        INTERNAL_SRAM_IA_R::new(((self.bits >> 14) & 0x0fff) as u16)
61    }
62    #[doc = "Bits 26:29"]
63    #[inline(always)]
64    pub fn internal_sram_mmu_multi_hit(&self) -> INTERNAL_SRAM_MMU_MULTI_HIT_R {
65        INTERNAL_SRAM_MMU_MULTI_HIT_R::new(((self.bits >> 26) & 0x0f) as u8)
66    }
67}
68#[cfg(feature = "impl-register-debug")]
69impl core::fmt::Debug for R {
70    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
71        f.debug_struct("MEM_ACCESS_DBUG0")
72            .field("pro_rom_mpu_ad", &self.pro_rom_mpu_ad())
73            .field("pro_rom_ia", &self.pro_rom_ia())
74            .field("app_rom_mpu_ad", &self.app_rom_mpu_ad())
75            .field("app_rom_ia", &self.app_rom_ia())
76            .field("share_rom_mpu_ad", &self.share_rom_mpu_ad())
77            .field("share_rom_ia", &self.share_rom_ia())
78            .field("internal_sram_mmu_ad", &self.internal_sram_mmu_ad())
79            .field("internal_sram_ia", &self.internal_sram_ia())
80            .field(
81                "internal_sram_mmu_multi_hit",
82                &self.internal_sram_mmu_multi_hit(),
83            )
84            .finish()
85    }
86}
87#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`mem_access_dbug0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
88pub struct MEM_ACCESS_DBUG0_SPEC;
89impl crate::RegisterSpec for MEM_ACCESS_DBUG0_SPEC {
90    type Ux = u32;
91}
92#[doc = "`read()` method returns [`mem_access_dbug0::R`](R) reader structure"]
93impl crate::Readable for MEM_ACCESS_DBUG0_SPEC {}
94#[doc = "`reset()` method sets MEM_ACCESS_DBUG0 to value 0"]
95impl crate::Resettable for MEM_ACCESS_DBUG0_SPEC {}
esp32/dport/mem_access_dbug0.rs

esp32/dport/
mem_access_dbug0.rs
