esp32/dport/
app_cache_lock_2_addr.rs

1#[doc = "Register `APP_CACHE_LOCK_2_ADDR` reader"]
2pub type R = crate::R<APP_CACHE_LOCK_2_ADDR_SPEC>;
3#[doc = "Register `APP_CACHE_LOCK_2_ADDR` writer"]
4pub type W = crate::W<APP_CACHE_LOCK_2_ADDR_SPEC>;
5#[doc = "Field `PRE` reader - "]
6pub type PRE_R = crate::FieldReader<u16>;
7#[doc = "Field `PRE` writer - "]
8pub type PRE_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>;
9#[doc = "Field `MIN` reader - "]
10pub type MIN_R = crate::FieldReader;
11#[doc = "Field `MIN` writer - "]
12pub type MIN_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
13#[doc = "Field `MAX` reader - "]
14pub type MAX_R = crate::FieldReader;
15#[doc = "Field `MAX` writer - "]
16pub type MAX_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
17impl R {
18    #[doc = "Bits 0:13"]
19    #[inline(always)]
20    pub fn pre(&self) -> PRE_R {
21        PRE_R::new((self.bits & 0x3fff) as u16)
22    }
23    #[doc = "Bits 14:17"]
24    #[inline(always)]
25    pub fn min(&self) -> MIN_R {
26        MIN_R::new(((self.bits >> 14) & 0x0f) as u8)
27    }
28    #[doc = "Bits 18:21"]
29    #[inline(always)]
30    pub fn max(&self) -> MAX_R {
31        MAX_R::new(((self.bits >> 18) & 0x0f) as u8)
32    }
33}
34#[cfg(feature = "impl-register-debug")]
35impl core::fmt::Debug for R {
36    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
37        f.debug_struct("APP_CACHE_LOCK_2_ADDR")
38            .field("pre", &self.pre())
39            .field("min", &self.min())
40            .field("max", &self.max())
41            .finish()
42    }
43}
44impl W {
45    #[doc = "Bits 0:13"]
46    #[inline(always)]
47    pub fn pre(&mut self) -> PRE_W<APP_CACHE_LOCK_2_ADDR_SPEC> {
48        PRE_W::new(self, 0)
49    }
50    #[doc = "Bits 14:17"]
51    #[inline(always)]
52    pub fn min(&mut self) -> MIN_W<APP_CACHE_LOCK_2_ADDR_SPEC> {
53        MIN_W::new(self, 14)
54    }
55    #[doc = "Bits 18:21"]
56    #[inline(always)]
57    pub fn max(&mut self) -> MAX_W<APP_CACHE_LOCK_2_ADDR_SPEC> {
58        MAX_W::new(self, 18)
59    }
60}
61#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`app_cache_lock_2_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_cache_lock_2_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
62pub struct APP_CACHE_LOCK_2_ADDR_SPEC;
63impl crate::RegisterSpec for APP_CACHE_LOCK_2_ADDR_SPEC {
64    type Ux = u32;
65}
66#[doc = "`read()` method returns [`app_cache_lock_2_addr::R`](R) reader structure"]
67impl crate::Readable for APP_CACHE_LOCK_2_ADDR_SPEC {}
68#[doc = "`write(|w| ..)` method takes [`app_cache_lock_2_addr::W`](W) writer structure"]
69impl crate::Writable for APP_CACHE_LOCK_2_ADDR_SPEC {
70    type Safety = crate::Unsafe;
71}
72#[doc = "`reset()` method sets APP_CACHE_LOCK_2_ADDR to value 0"]
73impl crate::Resettable for APP_CACHE_LOCK_2_ADDR_SPEC {}
esp32/dport/app_cache_lock_2_addr.rs

esp32/dport/
app_cache_lock_2_addr.rs
