esp32/sdhost/
hcon.rs

1#[doc = "Register `HCON` reader"]
2pub type R = crate::R<HCON_SPEC>;
3#[doc = "Field `CARD_TYPE` reader - Hardware support SDIO and MMC."]
4pub type CARD_TYPE_R = crate::BitReader;
5#[doc = "Field `CARD_NUM` reader - Support card number is 2."]
6pub type CARD_NUM_R = crate::FieldReader;
7#[doc = "Field `BUS_TYPE` reader - Register config is APB bus."]
8pub type BUS_TYPE_R = crate::BitReader;
9#[doc = "Field `DATA_WIDTH` reader - Regisger data widht is 32."]
10pub type DATA_WIDTH_R = crate::FieldReader;
11#[doc = "Field `ADDR_WIDTH` reader - Register address width is 32."]
12pub type ADDR_WIDTH_R = crate::FieldReader;
13#[doc = "Field `DMA_WIDTH` reader - DMA data witdth is 32."]
14pub type DMA_WIDTH_R = crate::FieldReader;
15#[doc = "Field `RAM_INDISE` reader - Inside RAM in SDMMC module."]
16pub type RAM_INDISE_R = crate::BitReader;
17#[doc = "Field `HOLD` reader - Have a hold regiser in data path ."]
18pub type HOLD_R = crate::BitReader;
19#[doc = "Field `NUM_CLK_DIV` reader - Have 4 clk divider in design ."]
20pub type NUM_CLK_DIV_R = crate::FieldReader;
21impl R {
22    #[doc = "Bit 0 - Hardware support SDIO and MMC."]
23    #[inline(always)]
24    pub fn card_type(&self) -> CARD_TYPE_R {
25        CARD_TYPE_R::new((self.bits & 1) != 0)
26    }
27    #[doc = "Bits 1:5 - Support card number is 2."]
28    #[inline(always)]
29    pub fn card_num(&self) -> CARD_NUM_R {
30        CARD_NUM_R::new(((self.bits >> 1) & 0x1f) as u8)
31    }
32    #[doc = "Bit 6 - Register config is APB bus."]
33    #[inline(always)]
34    pub fn bus_type(&self) -> BUS_TYPE_R {
35        BUS_TYPE_R::new(((self.bits >> 6) & 1) != 0)
36    }
37    #[doc = "Bits 7:9 - Regisger data widht is 32."]
38    #[inline(always)]
39    pub fn data_width(&self) -> DATA_WIDTH_R {
40        DATA_WIDTH_R::new(((self.bits >> 7) & 7) as u8)
41    }
42    #[doc = "Bits 10:15 - Register address width is 32."]
43    #[inline(always)]
44    pub fn addr_width(&self) -> ADDR_WIDTH_R {
45        ADDR_WIDTH_R::new(((self.bits >> 10) & 0x3f) as u8)
46    }
47    #[doc = "Bits 18:20 - DMA data witdth is 32."]
48    #[inline(always)]
49    pub fn dma_width(&self) -> DMA_WIDTH_R {
50        DMA_WIDTH_R::new(((self.bits >> 18) & 7) as u8)
51    }
52    #[doc = "Bit 21 - Inside RAM in SDMMC module."]
53    #[inline(always)]
54    pub fn ram_indise(&self) -> RAM_INDISE_R {
55        RAM_INDISE_R::new(((self.bits >> 21) & 1) != 0)
56    }
57    #[doc = "Bit 22 - Have a hold regiser in data path ."]
58    #[inline(always)]
59    pub fn hold(&self) -> HOLD_R {
60        HOLD_R::new(((self.bits >> 22) & 1) != 0)
61    }
62    #[doc = "Bits 24:25 - Have 4 clk divider in design ."]
63    #[inline(always)]
64    pub fn num_clk_div(&self) -> NUM_CLK_DIV_R {
65        NUM_CLK_DIV_R::new(((self.bits >> 24) & 3) as u8)
66    }
67}
68#[cfg(feature = "impl-register-debug")]
69impl core::fmt::Debug for R {
70    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
71        f.debug_struct("HCON")
72            .field("card_type", &self.card_type())
73            .field("card_num", &self.card_num())
74            .field("bus_type", &self.bus_type())
75            .field("data_width", &self.data_width())
76            .field("addr_width", &self.addr_width())
77            .field("dma_width", &self.dma_width())
78            .field("ram_indise", &self.ram_indise())
79            .field("hold", &self.hold())
80            .field("num_clk_div", &self.num_clk_div())
81            .finish()
82    }
83}
84#[doc = "Hardware feature register\n\nYou can [`read`](crate::Reg::read) this register and get [`hcon::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
85pub struct HCON_SPEC;
86impl crate::RegisterSpec for HCON_SPEC {
87    type Ux = u32;
88}
89#[doc = "`read()` method returns [`hcon::R`](R) reader structure"]
90impl crate::Readable for HCON_SPEC {}
91#[doc = "`reset()` method sets HCON to value 0x0344_4cc3"]
92impl crate::Resettable for HCON_SPEC {
93    const RESET_VALUE: u32 = 0x0344_4cc3;
94}
esp32/sdhost/hcon.rs

esp32/sdhost/
hcon.rs
