1#[doc = "Register `CMD` reader"]
2pub type R = crate::R<CMD_SPEC>;
3#[doc = "Register `CMD` writer"]
4pub type W = crate::W<CMD_SPEC>;
5#[doc = "Field `INDEX` reader - Command index."]
6pub type INDEX_R = crate::FieldReader;
7#[doc = "Field `INDEX` writer - Command index."]
8pub type INDEX_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
9#[doc = "Field `RESPONSE_EXPECT` reader - 0: No response expected from card; 1: Response expected from card."]
10pub type RESPONSE_EXPECT_R = crate::BitReader;
11#[doc = "Field `RESPONSE_EXPECT` writer - 0: No response expected from card; 1: Response expected from card."]
12pub type RESPONSE_EXPECT_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `RESPONSE_LENGTH` reader - 0: Short response expected from card; 1: Long response expected from card."]
14pub type RESPONSE_LENGTH_R = crate::BitReader;
15#[doc = "Field `RESPONSE_LENGTH` writer - 0: Short response expected from card; 1: Long response expected from card."]
16pub type RESPONSE_LENGTH_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `CHECK_RESPONSE_CRC` reader - 0: Do not check; 1: Check response CRC. Some of command responses do not return valid CRC bits. Software should disable CRC checks for those commands in order to disable CRC checking by controller."]
18pub type CHECK_RESPONSE_CRC_R = crate::BitReader;
19#[doc = "Field `CHECK_RESPONSE_CRC` writer - 0: Do not check; 1: Check response CRC. Some of command responses do not return valid CRC bits. Software should disable CRC checks for those commands in order to disable CRC checking by controller."]
20pub type CHECK_RESPONSE_CRC_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `DATA_EXPECTED` reader - 0: No data transfer expected; 1: Data transfer expected."]
22pub type DATA_EXPECTED_R = crate::BitReader;
23#[doc = "Field `DATA_EXPECTED` writer - 0: No data transfer expected; 1: Data transfer expected."]
24pub type DATA_EXPECTED_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `READ_WRITE` reader - 0: Read from card; 1: Write to card. Don't care if no data is expected from card."]
26pub type READ_WRITE_R = crate::BitReader;
27#[doc = "Field `READ_WRITE` writer - 0: Read from card; 1: Write to card. Don't care if no data is expected from card."]
28pub type READ_WRITE_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `TRANSFER_MODE` reader - Block data transfer command; 1: Stream data transfer command. Don't care if no data expected."]
30pub type TRANSFER_MODE_R = crate::BitReader;
31#[doc = "Field `TRANSFER_MODE` writer - Block data transfer command; 1: Stream data transfer command. Don't care if no data expected."]
32pub type TRANSFER_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `SEND_AUTO_STOP` reader - 0: No stop command is sent at the end of data transfer; 1: Send stop command at the end of data transfer."]
34pub type SEND_AUTO_STOP_R = crate::BitReader;
35#[doc = "Field `SEND_AUTO_STOP` writer - 0: No stop command is sent at the end of data transfer; 1: Send stop command at the end of data transfer."]
36pub type SEND_AUTO_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `WAIT_PRVDATA_COMPLETE` reader - 0: Send command at once, even if previous data transfer has not completed; 1: Wait for previous data transfer to complete before sending Command. The SDHOST_WAIT_PRVDATA_COMPLETE] = 0 option is typically used to query status of card during data transfer or to stop current data transfer. SDHOST_CARD_NUMBERr should be same as in previous command."]
38pub type WAIT_PRVDATA_COMPLETE_R = crate::BitReader;
39#[doc = "Field `WAIT_PRVDATA_COMPLETE` writer - 0: Send command at once, even if previous data transfer has not completed; 1: Wait for previous data transfer to complete before sending Command. The SDHOST_WAIT_PRVDATA_COMPLETE] = 0 option is typically used to query status of card during data transfer or to stop current data transfer. SDHOST_CARD_NUMBERr should be same as in previous command."]
40pub type WAIT_PRVDATA_COMPLETE_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `STOP_ABORT_CMD` reader - 0: Neither stop nor abort command can stop current data transfer. If abort is sent to function-number currently selected or not in data-transfer mode, then bit should be set to 0; 1: Stop or abort command intended to stop current data transfer in progress. When open-ended or predefined data transfer is in progress, and host issues stop or abort command to stop data transfer, bit should be set so that command/data state-machines of CIU can return correctly to idle state."]
42pub type STOP_ABORT_CMD_R = crate::BitReader;
43#[doc = "Field `STOP_ABORT_CMD` writer - 0: Neither stop nor abort command can stop current data transfer. If abort is sent to function-number currently selected or not in data-transfer mode, then bit should be set to 0; 1: Stop or abort command intended to stop current data transfer in progress. When open-ended or predefined data transfer is in progress, and host issues stop or abort command to stop data transfer, bit should be set so that command/data state-machines of CIU can return correctly to idle state."]
44pub type STOP_ABORT_CMD_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `SEND_INITIALIZATION` reader - 0: Do not send initialization sequence (80 clocks of 1) before sending this command; 1: Send initialization sequence before sending this command. After powered on, 80 clocks must be sent to card for initialization before sending any commands to card. Bit should be set while sending first command to card so that controller will initialize clocks before sending command to card."]
46pub type SEND_INITIALIZATION_R = crate::BitReader;
47#[doc = "Field `SEND_INITIALIZATION` writer - 0: Do not send initialization sequence (80 clocks of 1) before sending this command; 1: Send initialization sequence before sending this command. After powered on, 80 clocks must be sent to card for initialization before sending any commands to card. Bit should be set while sending first command to card so that controller will initialize clocks before sending command to card."]
48pub type SEND_INITIALIZATION_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `CARD_NUMBER` reader - Card number in use. Represents physical slot number of card being accessed. In SD-only mode, up to two cards are supported."]
50pub type CARD_NUMBER_R = crate::FieldReader;
51#[doc = "Field `CARD_NUMBER` writer - Card number in use. Represents physical slot number of card being accessed. In SD-only mode, up to two cards are supported."]
52pub type CARD_NUMBER_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
53#[doc = "Field `UPDATE_CLOCK_REGISTERS_ONLY` reader - 0: Normal command sequence; 1: Do not send commands, just update clock register value into card clock domain. Following register values are transferred into card clock domain: CLKDIV, CLRSRC, and CLKENA. Changes card clocks (change frequency, truncate off or on, and set low-frequency mode). This is provided in order to change clock frequency or stop clock without having to send command to cards. During normal command sequence, when sdhost_update_clock_registers_only = 0, following control registers are transferred from BIU to CIU: CMD, CMDARG, TMOUT, CTYPE, BLKSIZ, and BYTCNT. CIU uses new register values for new command sequence to card(s). When bit is set, there are no Command Done interrupts because no command is sent to SD_MMC_CEATA cards."]
54pub type UPDATE_CLOCK_REGISTERS_ONLY_R = crate::BitReader;
55#[doc = "Field `UPDATE_CLOCK_REGISTERS_ONLY` writer - 0: Normal command sequence; 1: Do not send commands, just update clock register value into card clock domain. Following register values are transferred into card clock domain: CLKDIV, CLRSRC, and CLKENA. Changes card clocks (change frequency, truncate off or on, and set low-frequency mode). This is provided in order to change clock frequency or stop clock without having to send command to cards. During normal command sequence, when sdhost_update_clock_registers_only = 0, following control registers are transferred from BIU to CIU: CMD, CMDARG, TMOUT, CTYPE, BLKSIZ, and BYTCNT. CIU uses new register values for new command sequence to card(s). When bit is set, there are no Command Done interrupts because no command is sent to SD_MMC_CEATA cards."]
56pub type UPDATE_CLOCK_REGISTERS_ONLY_W<'a, REG> = crate::BitWriter<'a, REG>;
57#[doc = "Field `READ_CEATA_DEVICE` reader - Read access flag. 0: Host is not performing read access (RW_REG or RW_BLK)towards CE-ATA device; 1: Host is performing read access (RW_REG or RW_BLK) towards CE-ATA device. Software should set this bit to indicate that CE-ATA device is being accessed for read transfer. This bit is used to disable read data timeout indication while performing CE-ATA read transfers. Maximum value of I/O transmission delay can be no less than 10 seconds. SD/MMC should not indicate read data timeout while waiting for data from CE-ATA device."]
58pub type READ_CEATA_DEVICE_R = crate::BitReader;
59#[doc = "Field `READ_CEATA_DEVICE` writer - Read access flag. 0: Host is not performing read access (RW_REG or RW_BLK)towards CE-ATA device; 1: Host is performing read access (RW_REG or RW_BLK) towards CE-ATA device. Software should set this bit to indicate that CE-ATA device is being accessed for read transfer. This bit is used to disable read data timeout indication while performing CE-ATA read transfers. Maximum value of I/O transmission delay can be no less than 10 seconds. SD/MMC should not indicate read data timeout while waiting for data from CE-ATA device."]
60pub type READ_CEATA_DEVICE_W<'a, REG> = crate::BitWriter<'a, REG>;
61#[doc = "Field `CCS_EXPECTED` reader - Expected Command Completion Signal (CCS) configuration. 0: Interrupts are not enabled in CE-ATA device (nIEN = 1 in ATA control register), or command does not expect CCS from device; 1: Interrupts are enabled in CE-ATA device (nIEN = 0), and RW_BLK command expects command completion signal from CE-ATA device. If the command expects Command Completion Signal (CCS) from the CE-ATA device, the software should set this control bit. SD/MMC sets Data Transfer Over (DTO) bit in RINTSTS register and generates interrupt to host if Data Transfer Over interrupt is not masked."]
62pub type CCS_EXPECTED_R = crate::BitReader;
63#[doc = "Field `CCS_EXPECTED` writer - Expected Command Completion Signal (CCS) configuration. 0: Interrupts are not enabled in CE-ATA device (nIEN = 1 in ATA control register), or command does not expect CCS from device; 1: Interrupts are enabled in CE-ATA device (nIEN = 0), and RW_BLK command expects command completion signal from CE-ATA device. If the command expects Command Completion Signal (CCS) from the CE-ATA device, the software should set this control bit. SD/MMC sets Data Transfer Over (DTO) bit in RINTSTS register and generates interrupt to host if Data Transfer Over interrupt is not masked."]
64pub type CCS_EXPECTED_W<'a, REG> = crate::BitWriter<'a, REG>;
65#[doc = "Field `USE_HOLE` reader - Use Hold Register. 0: CMD and DATA sent to card bypassing HOLD Register; 1: CMD and DATA sent to card through the HOLD Register."]
66pub type USE_HOLE_R = crate::BitReader;
67#[doc = "Field `USE_HOLE` writer - Use Hold Register. 0: CMD and DATA sent to card bypassing HOLD Register; 1: CMD and DATA sent to card through the HOLD Register."]
68pub type USE_HOLE_W<'a, REG> = crate::BitWriter<'a, REG>;
69#[doc = "Field `START_CMD` reader - Start command. Once command is served by the CIU, this bit is automatically cleared. When this bit is set, host should not attempt to write to any command registers. If a write is attempted, hardware lock error is set in raw interrupt register. Once command is sent and a response is received from SD_MMC_CEATA cards, Command Done bit is set in the raw interrupt Register."]
70pub type START_CMD_R = crate::BitReader;
71#[doc = "Field `START_CMD` writer - Start command. Once command is served by the CIU, this bit is automatically cleared. When this bit is set, host should not attempt to write to any command registers. If a write is attempted, hardware lock error is set in raw interrupt register. Once command is sent and a response is received from SD_MMC_CEATA cards, Command Done bit is set in the raw interrupt Register."]
72pub type START_CMD_W<'a, REG> = crate::BitWriter<'a, REG>;
73impl R {
74 #[doc = "Bits 0:5 - Command index."]
75 #[inline(always)]
76 pub fn index(&self) -> INDEX_R {
77 INDEX_R::new((self.bits & 0x3f) as u8)
78 }
79 #[doc = "Bit 6 - 0: No response expected from card; 1: Response expected from card."]
80 #[inline(always)]
81 pub fn response_expect(&self) -> RESPONSE_EXPECT_R {
82 RESPONSE_EXPECT_R::new(((self.bits >> 6) & 1) != 0)
83 }
84 #[doc = "Bit 7 - 0: Short response expected from card; 1: Long response expected from card."]
85 #[inline(always)]
86 pub fn response_length(&self) -> RESPONSE_LENGTH_R {
87 RESPONSE_LENGTH_R::new(((self.bits >> 7) & 1) != 0)
88 }
89 #[doc = "Bit 8 - 0: Do not check; 1: Check response CRC. Some of command responses do not return valid CRC bits. Software should disable CRC checks for those commands in order to disable CRC checking by controller."]
90 #[inline(always)]
91 pub fn check_response_crc(&self) -> CHECK_RESPONSE_CRC_R {
92 CHECK_RESPONSE_CRC_R::new(((self.bits >> 8) & 1) != 0)
93 }
94 #[doc = "Bit 9 - 0: No data transfer expected; 1: Data transfer expected."]
95 #[inline(always)]
96 pub fn data_expected(&self) -> DATA_EXPECTED_R {
97 DATA_EXPECTED_R::new(((self.bits >> 9) & 1) != 0)
98 }
99 #[doc = "Bit 10 - 0: Read from card; 1: Write to card. Don't care if no data is expected from card."]
100 #[inline(always)]
101 pub fn read_write(&self) -> READ_WRITE_R {
102 READ_WRITE_R::new(((self.bits >> 10) & 1) != 0)
103 }
104 #[doc = "Bit 11 - Block data transfer command; 1: Stream data transfer command. Don't care if no data expected."]
105 #[inline(always)]
106 pub fn transfer_mode(&self) -> TRANSFER_MODE_R {
107 TRANSFER_MODE_R::new(((self.bits >> 11) & 1) != 0)
108 }
109 #[doc = "Bit 12 - 0: No stop command is sent at the end of data transfer; 1: Send stop command at the end of data transfer."]
110 #[inline(always)]
111 pub fn send_auto_stop(&self) -> SEND_AUTO_STOP_R {
112 SEND_AUTO_STOP_R::new(((self.bits >> 12) & 1) != 0)
113 }
114 #[doc = "Bit 13 - 0: Send command at once, even if previous data transfer has not completed; 1: Wait for previous data transfer to complete before sending Command. The SDHOST_WAIT_PRVDATA_COMPLETE] = 0 option is typically used to query status of card during data transfer or to stop current data transfer. SDHOST_CARD_NUMBERr should be same as in previous command."]
115 #[inline(always)]
116 pub fn wait_prvdata_complete(&self) -> WAIT_PRVDATA_COMPLETE_R {
117 WAIT_PRVDATA_COMPLETE_R::new(((self.bits >> 13) & 1) != 0)
118 }
119 #[doc = "Bit 14 - 0: Neither stop nor abort command can stop current data transfer. If abort is sent to function-number currently selected or not in data-transfer mode, then bit should be set to 0; 1: Stop or abort command intended to stop current data transfer in progress. When open-ended or predefined data transfer is in progress, and host issues stop or abort command to stop data transfer, bit should be set so that command/data state-machines of CIU can return correctly to idle state."]
120 #[inline(always)]
121 pub fn stop_abort_cmd(&self) -> STOP_ABORT_CMD_R {
122 STOP_ABORT_CMD_R::new(((self.bits >> 14) & 1) != 0)
123 }
124 #[doc = "Bit 15 - 0: Do not send initialization sequence (80 clocks of 1) before sending this command; 1: Send initialization sequence before sending this command. After powered on, 80 clocks must be sent to card for initialization before sending any commands to card. Bit should be set while sending first command to card so that controller will initialize clocks before sending command to card."]
125 #[inline(always)]
126 pub fn send_initialization(&self) -> SEND_INITIALIZATION_R {
127 SEND_INITIALIZATION_R::new(((self.bits >> 15) & 1) != 0)
128 }
129 #[doc = "Bits 16:20 - Card number in use. Represents physical slot number of card being accessed. In SD-only mode, up to two cards are supported."]
130 #[inline(always)]
131 pub fn card_number(&self) -> CARD_NUMBER_R {
132 CARD_NUMBER_R::new(((self.bits >> 16) & 0x1f) as u8)
133 }
134 #[doc = "Bit 21 - 0: Normal command sequence; 1: Do not send commands, just update clock register value into card clock domain. Following register values are transferred into card clock domain: CLKDIV, CLRSRC, and CLKENA. Changes card clocks (change frequency, truncate off or on, and set low-frequency mode). This is provided in order to change clock frequency or stop clock without having to send command to cards. During normal command sequence, when sdhost_update_clock_registers_only = 0, following control registers are transferred from BIU to CIU: CMD, CMDARG, TMOUT, CTYPE, BLKSIZ, and BYTCNT. CIU uses new register values for new command sequence to card(s). When bit is set, there are no Command Done interrupts because no command is sent to SD_MMC_CEATA cards."]
135 #[inline(always)]
136 pub fn update_clock_registers_only(&self) -> UPDATE_CLOCK_REGISTERS_ONLY_R {
137 UPDATE_CLOCK_REGISTERS_ONLY_R::new(((self.bits >> 21) & 1) != 0)
138 }
139 #[doc = "Bit 22 - Read access flag. 0: Host is not performing read access (RW_REG or RW_BLK)towards CE-ATA device; 1: Host is performing read access (RW_REG or RW_BLK) towards CE-ATA device. Software should set this bit to indicate that CE-ATA device is being accessed for read transfer. This bit is used to disable read data timeout indication while performing CE-ATA read transfers. Maximum value of I/O transmission delay can be no less than 10 seconds. SD/MMC should not indicate read data timeout while waiting for data from CE-ATA device."]
140 #[inline(always)]
141 pub fn read_ceata_device(&self) -> READ_CEATA_DEVICE_R {
142 READ_CEATA_DEVICE_R::new(((self.bits >> 22) & 1) != 0)
143 }
144 #[doc = "Bit 23 - Expected Command Completion Signal (CCS) configuration. 0: Interrupts are not enabled in CE-ATA device (nIEN = 1 in ATA control register), or command does not expect CCS from device; 1: Interrupts are enabled in CE-ATA device (nIEN = 0), and RW_BLK command expects command completion signal from CE-ATA device. If the command expects Command Completion Signal (CCS) from the CE-ATA device, the software should set this control bit. SD/MMC sets Data Transfer Over (DTO) bit in RINTSTS register and generates interrupt to host if Data Transfer Over interrupt is not masked."]
145 #[inline(always)]
146 pub fn ccs_expected(&self) -> CCS_EXPECTED_R {
147 CCS_EXPECTED_R::new(((self.bits >> 23) & 1) != 0)
148 }
149 #[doc = "Bit 29 - Use Hold Register. 0: CMD and DATA sent to card bypassing HOLD Register; 1: CMD and DATA sent to card through the HOLD Register."]
150 #[inline(always)]
151 pub fn use_hole(&self) -> USE_HOLE_R {
152 USE_HOLE_R::new(((self.bits >> 29) & 1) != 0)
153 }
154 #[doc = "Bit 31 - Start command. Once command is served by the CIU, this bit is automatically cleared. When this bit is set, host should not attempt to write to any command registers. If a write is attempted, hardware lock error is set in raw interrupt register. Once command is sent and a response is received from SD_MMC_CEATA cards, Command Done bit is set in the raw interrupt Register."]
155 #[inline(always)]
156 pub fn start_cmd(&self) -> START_CMD_R {
157 START_CMD_R::new(((self.bits >> 31) & 1) != 0)
158 }
159}
160#[cfg(feature = "impl-register-debug")]
161impl core::fmt::Debug for R {
162 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
163 f.debug_struct("CMD")
164 .field("index", &self.index())
165 .field("response_expect", &self.response_expect())
166 .field("response_length", &self.response_length())
167 .field("check_response_crc", &self.check_response_crc())
168 .field("data_expected", &self.data_expected())
169 .field("read_write", &self.read_write())
170 .field("transfer_mode", &self.transfer_mode())
171 .field("send_auto_stop", &self.send_auto_stop())
172 .field("wait_prvdata_complete", &self.wait_prvdata_complete())
173 .field("stop_abort_cmd", &self.stop_abort_cmd())
174 .field("send_initialization", &self.send_initialization())
175 .field("card_number", &self.card_number())
176 .field(
177 "update_clock_registers_only",
178 &self.update_clock_registers_only(),
179 )
180 .field("read_ceata_device", &self.read_ceata_device())
181 .field("ccs_expected", &self.ccs_expected())
182 .field("use_hole", &self.use_hole())
183 .field("start_cmd", &self.start_cmd())
184 .finish()
185 }
186}
187impl W {
188 #[doc = "Bits 0:5 - Command index."]
189 #[inline(always)]
190 pub fn index(&mut self) -> INDEX_W<CMD_SPEC> {
191 INDEX_W::new(self, 0)
192 }
193 #[doc = "Bit 6 - 0: No response expected from card; 1: Response expected from card."]
194 #[inline(always)]
195 pub fn response_expect(&mut self) -> RESPONSE_EXPECT_W<CMD_SPEC> {
196 RESPONSE_EXPECT_W::new(self, 6)
197 }
198 #[doc = "Bit 7 - 0: Short response expected from card; 1: Long response expected from card."]
199 #[inline(always)]
200 pub fn response_length(&mut self) -> RESPONSE_LENGTH_W<CMD_SPEC> {
201 RESPONSE_LENGTH_W::new(self, 7)
202 }
203 #[doc = "Bit 8 - 0: Do not check; 1: Check response CRC. Some of command responses do not return valid CRC bits. Software should disable CRC checks for those commands in order to disable CRC checking by controller."]
204 #[inline(always)]
205 pub fn check_response_crc(&mut self) -> CHECK_RESPONSE_CRC_W<CMD_SPEC> {
206 CHECK_RESPONSE_CRC_W::new(self, 8)
207 }
208 #[doc = "Bit 9 - 0: No data transfer expected; 1: Data transfer expected."]
209 #[inline(always)]
210 pub fn data_expected(&mut self) -> DATA_EXPECTED_W<CMD_SPEC> {
211 DATA_EXPECTED_W::new(self, 9)
212 }
213 #[doc = "Bit 10 - 0: Read from card; 1: Write to card. Don't care if no data is expected from card."]
214 #[inline(always)]
215 pub fn read_write(&mut self) -> READ_WRITE_W<CMD_SPEC> {
216 READ_WRITE_W::new(self, 10)
217 }
218 #[doc = "Bit 11 - Block data transfer command; 1: Stream data transfer command. Don't care if no data expected."]
219 #[inline(always)]
220 pub fn transfer_mode(&mut self) -> TRANSFER_MODE_W<CMD_SPEC> {
221 TRANSFER_MODE_W::new(self, 11)
222 }
223 #[doc = "Bit 12 - 0: No stop command is sent at the end of data transfer; 1: Send stop command at the end of data transfer."]
224 #[inline(always)]
225 pub fn send_auto_stop(&mut self) -> SEND_AUTO_STOP_W<CMD_SPEC> {
226 SEND_AUTO_STOP_W::new(self, 12)
227 }
228 #[doc = "Bit 13 - 0: Send command at once, even if previous data transfer has not completed; 1: Wait for previous data transfer to complete before sending Command. The SDHOST_WAIT_PRVDATA_COMPLETE] = 0 option is typically used to query status of card during data transfer or to stop current data transfer. SDHOST_CARD_NUMBERr should be same as in previous command."]
229 #[inline(always)]
230 pub fn wait_prvdata_complete(&mut self) -> WAIT_PRVDATA_COMPLETE_W<CMD_SPEC> {
231 WAIT_PRVDATA_COMPLETE_W::new(self, 13)
232 }
233 #[doc = "Bit 14 - 0: Neither stop nor abort command can stop current data transfer. If abort is sent to function-number currently selected or not in data-transfer mode, then bit should be set to 0; 1: Stop or abort command intended to stop current data transfer in progress. When open-ended or predefined data transfer is in progress, and host issues stop or abort command to stop data transfer, bit should be set so that command/data state-machines of CIU can return correctly to idle state."]
234 #[inline(always)]
235 pub fn stop_abort_cmd(&mut self) -> STOP_ABORT_CMD_W<CMD_SPEC> {
236 STOP_ABORT_CMD_W::new(self, 14)
237 }
238 #[doc = "Bit 15 - 0: Do not send initialization sequence (80 clocks of 1) before sending this command; 1: Send initialization sequence before sending this command. After powered on, 80 clocks must be sent to card for initialization before sending any commands to card. Bit should be set while sending first command to card so that controller will initialize clocks before sending command to card."]
239 #[inline(always)]
240 pub fn send_initialization(&mut self) -> SEND_INITIALIZATION_W<CMD_SPEC> {
241 SEND_INITIALIZATION_W::new(self, 15)
242 }
243 #[doc = "Bits 16:20 - Card number in use. Represents physical slot number of card being accessed. In SD-only mode, up to two cards are supported."]
244 #[inline(always)]
245 pub fn card_number(&mut self) -> CARD_NUMBER_W<CMD_SPEC> {
246 CARD_NUMBER_W::new(self, 16)
247 }
248 #[doc = "Bit 21 - 0: Normal command sequence; 1: Do not send commands, just update clock register value into card clock domain. Following register values are transferred into card clock domain: CLKDIV, CLRSRC, and CLKENA. Changes card clocks (change frequency, truncate off or on, and set low-frequency mode). This is provided in order to change clock frequency or stop clock without having to send command to cards. During normal command sequence, when sdhost_update_clock_registers_only = 0, following control registers are transferred from BIU to CIU: CMD, CMDARG, TMOUT, CTYPE, BLKSIZ, and BYTCNT. CIU uses new register values for new command sequence to card(s). When bit is set, there are no Command Done interrupts because no command is sent to SD_MMC_CEATA cards."]
249 #[inline(always)]
250 pub fn update_clock_registers_only(&mut self) -> UPDATE_CLOCK_REGISTERS_ONLY_W<CMD_SPEC> {
251 UPDATE_CLOCK_REGISTERS_ONLY_W::new(self, 21)
252 }
253 #[doc = "Bit 22 - Read access flag. 0: Host is not performing read access (RW_REG or RW_BLK)towards CE-ATA device; 1: Host is performing read access (RW_REG or RW_BLK) towards CE-ATA device. Software should set this bit to indicate that CE-ATA device is being accessed for read transfer. This bit is used to disable read data timeout indication while performing CE-ATA read transfers. Maximum value of I/O transmission delay can be no less than 10 seconds. SD/MMC should not indicate read data timeout while waiting for data from CE-ATA device."]
254 #[inline(always)]
255 pub fn read_ceata_device(&mut self) -> READ_CEATA_DEVICE_W<CMD_SPEC> {
256 READ_CEATA_DEVICE_W::new(self, 22)
257 }
258 #[doc = "Bit 23 - Expected Command Completion Signal (CCS) configuration. 0: Interrupts are not enabled in CE-ATA device (nIEN = 1 in ATA control register), or command does not expect CCS from device; 1: Interrupts are enabled in CE-ATA device (nIEN = 0), and RW_BLK command expects command completion signal from CE-ATA device. If the command expects Command Completion Signal (CCS) from the CE-ATA device, the software should set this control bit. SD/MMC sets Data Transfer Over (DTO) bit in RINTSTS register and generates interrupt to host if Data Transfer Over interrupt is not masked."]
259 #[inline(always)]
260 pub fn ccs_expected(&mut self) -> CCS_EXPECTED_W<CMD_SPEC> {
261 CCS_EXPECTED_W::new(self, 23)
262 }
263 #[doc = "Bit 29 - Use Hold Register. 0: CMD and DATA sent to card bypassing HOLD Register; 1: CMD and DATA sent to card through the HOLD Register."]
264 #[inline(always)]
265 pub fn use_hole(&mut self) -> USE_HOLE_W<CMD_SPEC> {
266 USE_HOLE_W::new(self, 29)
267 }
268 #[doc = "Bit 31 - Start command. Once command is served by the CIU, this bit is automatically cleared. When this bit is set, host should not attempt to write to any command registers. If a write is attempted, hardware lock error is set in raw interrupt register. Once command is sent and a response is received from SD_MMC_CEATA cards, Command Done bit is set in the raw interrupt Register."]
269 #[inline(always)]
270 pub fn start_cmd(&mut self) -> START_CMD_W<CMD_SPEC> {
271 START_CMD_W::new(self, 31)
272 }
273}
274#[doc = "Command and boot configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
275pub struct CMD_SPEC;
276impl crate::RegisterSpec for CMD_SPEC {
277 type Ux = u32;
278}
279#[doc = "`read()` method returns [`cmd::R`](R) reader structure"]
280impl crate::Readable for CMD_SPEC {}
281#[doc = "`write(|w| ..)` method takes [`cmd::W`](W) writer structure"]
282impl crate::Writable for CMD_SPEC {
283 type Safety = crate::Unsafe;
284 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
285 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
286}
287#[doc = "`reset()` method sets CMD to value 0x2000_0000"]
288impl crate::Resettable for CMD_SPEC {
289 const RESET_VALUE: u32 = 0x2000_0000;
290}