esp32/rtc_i2c/
int_raw.rs

1#[doc = "Register `INT_RAW` reader"]
2pub type R = crate::R<INT_RAW_SPEC>;
3#[doc = "Register `INT_RAW` writer"]
4pub type W = crate::W<INT_RAW_SPEC>;
5#[doc = "Field `SLAVE_TRANS_COMPLETE` reader - Slave accepted 1 byte and address matched"]
6pub type SLAVE_TRANS_COMPLETE_R = crate::BitReader;
7#[doc = "Field `SLAVE_TRANS_COMPLETE` writer - Slave accepted 1 byte and address matched"]
8pub type SLAVE_TRANS_COMPLETE_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `ARBITRATION_LOST` reader - Master lost arbitration"]
10pub type ARBITRATION_LOST_R = crate::BitReader;
11#[doc = "Field `ARBITRATION_LOST` writer - Master lost arbitration"]
12pub type ARBITRATION_LOST_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `MASTER_TRANS_COMPLETE` reader - "]
14pub type MASTER_TRANS_COMPLETE_R = crate::BitReader;
15#[doc = "Field `MASTER_TRANS_COMPLETE` writer - "]
16pub type MASTER_TRANS_COMPLETE_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `TRANS_COMPLETE` reader - Stop condition has been detected interrupt raw status"]
18pub type TRANS_COMPLETE_R = crate::BitReader;
19#[doc = "Field `TRANS_COMPLETE` writer - Stop condition has been detected interrupt raw status"]
20pub type TRANS_COMPLETE_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `TIME_OUT` reader - time out interrupt raw status"]
22pub type TIME_OUT_R = crate::BitReader;
23impl R {
24    #[doc = "Bit 3 - Slave accepted 1 byte and address matched"]
25    #[inline(always)]
26    pub fn slave_trans_complete(&self) -> SLAVE_TRANS_COMPLETE_R {
27        SLAVE_TRANS_COMPLETE_R::new(((self.bits >> 3) & 1) != 0)
28    }
29    #[doc = "Bit 4 - Master lost arbitration"]
30    #[inline(always)]
31    pub fn arbitration_lost(&self) -> ARBITRATION_LOST_R {
32        ARBITRATION_LOST_R::new(((self.bits >> 4) & 1) != 0)
33    }
34    #[doc = "Bit 5"]
35    #[inline(always)]
36    pub fn master_trans_complete(&self) -> MASTER_TRANS_COMPLETE_R {
37        MASTER_TRANS_COMPLETE_R::new(((self.bits >> 5) & 1) != 0)
38    }
39    #[doc = "Bit 6 - Stop condition has been detected interrupt raw status"]
40    #[inline(always)]
41    pub fn trans_complete(&self) -> TRANS_COMPLETE_R {
42        TRANS_COMPLETE_R::new(((self.bits >> 6) & 1) != 0)
43    }
44    #[doc = "Bit 7 - time out interrupt raw status"]
45    #[inline(always)]
46    pub fn time_out(&self) -> TIME_OUT_R {
47        TIME_OUT_R::new(((self.bits >> 7) & 1) != 0)
48    }
49}
50#[cfg(feature = "impl-register-debug")]
51impl core::fmt::Debug for R {
52    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
53        f.debug_struct("INT_RAW")
54            .field("slave_trans_complete", &self.slave_trans_complete())
55            .field("arbitration_lost", &self.arbitration_lost())
56            .field("master_trans_complete", &self.master_trans_complete())
57            .field("trans_complete", &self.trans_complete())
58            .field("time_out", &self.time_out())
59            .finish()
60    }
61}
62impl W {
63    #[doc = "Bit 3 - Slave accepted 1 byte and address matched"]
64    #[inline(always)]
65    pub fn slave_trans_complete(&mut self) -> SLAVE_TRANS_COMPLETE_W<INT_RAW_SPEC> {
66        SLAVE_TRANS_COMPLETE_W::new(self, 3)
67    }
68    #[doc = "Bit 4 - Master lost arbitration"]
69    #[inline(always)]
70    pub fn arbitration_lost(&mut self) -> ARBITRATION_LOST_W<INT_RAW_SPEC> {
71        ARBITRATION_LOST_W::new(self, 4)
72    }
73    #[doc = "Bit 5"]
74    #[inline(always)]
75    pub fn master_trans_complete(&mut self) -> MASTER_TRANS_COMPLETE_W<INT_RAW_SPEC> {
76        MASTER_TRANS_COMPLETE_W::new(self, 5)
77    }
78    #[doc = "Bit 6 - Stop condition has been detected interrupt raw status"]
79    #[inline(always)]
80    pub fn trans_complete(&mut self) -> TRANS_COMPLETE_W<INT_RAW_SPEC> {
81        TRANS_COMPLETE_W::new(self, 6)
82    }
83}
84#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`int_raw::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_raw::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
85pub struct INT_RAW_SPEC;
86impl crate::RegisterSpec for INT_RAW_SPEC {
87    type Ux = u32;
88}
89#[doc = "`read()` method returns [`int_raw::R`](R) reader structure"]
90impl crate::Readable for INT_RAW_SPEC {}
91#[doc = "`write(|w| ..)` method takes [`int_raw::W`](W) writer structure"]
92impl crate::Writable for INT_RAW_SPEC {
93    type Safety = crate::Unsafe;
94    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
95    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
96}
97#[doc = "`reset()` method sets INT_RAW to value 0"]
98impl crate::Resettable for INT_RAW_SPEC {
99    const RESET_VALUE: u32 = 0;
100}
esp32/rtc_i2c/int_raw.rs

esp32/rtc_i2c/
int_raw.rs
