esp32/rtc_i2c/
ctrl.rs

1#[doc = "Register `CTRL` reader"]
2pub type R = crate::R<CTRL_SPEC>;
3#[doc = "Register `CTRL` writer"]
4pub type W = crate::W<CTRL_SPEC>;
5#[doc = "Field `SDA_FORCE_OUT` reader - SDA is push-pull (1) or open-drain (0)"]
6pub type SDA_FORCE_OUT_R = crate::BitReader;
7#[doc = "Field `SDA_FORCE_OUT` writer - SDA is push-pull (1) or open-drain (0)"]
8pub type SDA_FORCE_OUT_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `SCL_FORCE_OUT` reader - SCL is push-pull (1) or open-drain (0)"]
10pub type SCL_FORCE_OUT_R = crate::BitReader;
11#[doc = "Field `SCL_FORCE_OUT` writer - SCL is push-pull (1) or open-drain (0)"]
12pub type SCL_FORCE_OUT_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `MS_MODE` reader - Master (1) or slave (0)"]
14pub type MS_MODE_R = crate::BitReader;
15#[doc = "Field `MS_MODE` writer - Master (1) or slave (0)"]
16pub type MS_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `TRANS_START` reader - Force to generate start condition"]
18pub type TRANS_START_R = crate::BitReader;
19#[doc = "Field `TRANS_START` writer - Force to generate start condition"]
20pub type TRANS_START_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `TX_LSB_FIRST` reader - Send LSB first"]
22pub type TX_LSB_FIRST_R = crate::BitReader;
23#[doc = "Field `TX_LSB_FIRST` writer - Send LSB first"]
24pub type TX_LSB_FIRST_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `RX_LSB_FIRST` reader - Receive LSB first"]
26pub type RX_LSB_FIRST_R = crate::BitReader;
27#[doc = "Field `RX_LSB_FIRST` writer - Receive LSB first"]
28pub type RX_LSB_FIRST_W<'a, REG> = crate::BitWriter<'a, REG>;
29impl R {
30    #[doc = "Bit 0 - SDA is push-pull (1) or open-drain (0)"]
31    #[inline(always)]
32    pub fn sda_force_out(&self) -> SDA_FORCE_OUT_R {
33        SDA_FORCE_OUT_R::new((self.bits & 1) != 0)
34    }
35    #[doc = "Bit 1 - SCL is push-pull (1) or open-drain (0)"]
36    #[inline(always)]
37    pub fn scl_force_out(&self) -> SCL_FORCE_OUT_R {
38        SCL_FORCE_OUT_R::new(((self.bits >> 1) & 1) != 0)
39    }
40    #[doc = "Bit 4 - Master (1) or slave (0)"]
41    #[inline(always)]
42    pub fn ms_mode(&self) -> MS_MODE_R {
43        MS_MODE_R::new(((self.bits >> 4) & 1) != 0)
44    }
45    #[doc = "Bit 5 - Force to generate start condition"]
46    #[inline(always)]
47    pub fn trans_start(&self) -> TRANS_START_R {
48        TRANS_START_R::new(((self.bits >> 5) & 1) != 0)
49    }
50    #[doc = "Bit 6 - Send LSB first"]
51    #[inline(always)]
52    pub fn tx_lsb_first(&self) -> TX_LSB_FIRST_R {
53        TX_LSB_FIRST_R::new(((self.bits >> 6) & 1) != 0)
54    }
55    #[doc = "Bit 7 - Receive LSB first"]
56    #[inline(always)]
57    pub fn rx_lsb_first(&self) -> RX_LSB_FIRST_R {
58        RX_LSB_FIRST_R::new(((self.bits >> 7) & 1) != 0)
59    }
60}
61#[cfg(feature = "impl-register-debug")]
62impl core::fmt::Debug for R {
63    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
64        f.debug_struct("CTRL")
65            .field("sda_force_out", &self.sda_force_out())
66            .field("scl_force_out", &self.scl_force_out())
67            .field("ms_mode", &self.ms_mode())
68            .field("trans_start", &self.trans_start())
69            .field("tx_lsb_first", &self.tx_lsb_first())
70            .field("rx_lsb_first", &self.rx_lsb_first())
71            .finish()
72    }
73}
74impl W {
75    #[doc = "Bit 0 - SDA is push-pull (1) or open-drain (0)"]
76    #[inline(always)]
77    pub fn sda_force_out(&mut self) -> SDA_FORCE_OUT_W<CTRL_SPEC> {
78        SDA_FORCE_OUT_W::new(self, 0)
79    }
80    #[doc = "Bit 1 - SCL is push-pull (1) or open-drain (0)"]
81    #[inline(always)]
82    pub fn scl_force_out(&mut self) -> SCL_FORCE_OUT_W<CTRL_SPEC> {
83        SCL_FORCE_OUT_W::new(self, 1)
84    }
85    #[doc = "Bit 4 - Master (1) or slave (0)"]
86    #[inline(always)]
87    pub fn ms_mode(&mut self) -> MS_MODE_W<CTRL_SPEC> {
88        MS_MODE_W::new(self, 4)
89    }
90    #[doc = "Bit 5 - Force to generate start condition"]
91    #[inline(always)]
92    pub fn trans_start(&mut self) -> TRANS_START_W<CTRL_SPEC> {
93        TRANS_START_W::new(self, 5)
94    }
95    #[doc = "Bit 6 - Send LSB first"]
96    #[inline(always)]
97    pub fn tx_lsb_first(&mut self) -> TX_LSB_FIRST_W<CTRL_SPEC> {
98        TX_LSB_FIRST_W::new(self, 6)
99    }
100    #[doc = "Bit 7 - Receive LSB first"]
101    #[inline(always)]
102    pub fn rx_lsb_first(&mut self) -> RX_LSB_FIRST_W<CTRL_SPEC> {
103        RX_LSB_FIRST_W::new(self, 7)
104    }
105}
106#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
107pub struct CTRL_SPEC;
108impl crate::RegisterSpec for CTRL_SPEC {
109    type Ux = u32;
110}
111#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"]
112impl crate::Readable for CTRL_SPEC {}
113#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"]
114impl crate::Writable for CTRL_SPEC {
115    type Safety = crate::Unsafe;
116    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
117    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
118}
119#[doc = "`reset()` method sets CTRL to value 0"]
120impl crate::Resettable for CTRL_SPEC {
121    const RESET_VALUE: u32 = 0;
122}
esp32/rtc_i2c/ctrl.rs

esp32/rtc_i2c/
ctrl.rs
