esp32/dport/
cpu_per_conf.rs

1#[doc = "Register `CPU_PER_CONF` reader"]
2pub type R = crate::R<CPU_PER_CONF_SPEC>;
3#[doc = "Register `CPU_PER_CONF` writer"]
4pub type W = crate::W<CPU_PER_CONF_SPEC>;
5#[doc = "Field `CPUPERIOD_SEL` reader - "]
6pub type CPUPERIOD_SEL_R = crate::FieldReader;
7#[doc = "Field `CPUPERIOD_SEL` writer - "]
8pub type CPUPERIOD_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
9#[doc = "Field `LOWSPEED_CLK_SEL` reader - "]
10pub type LOWSPEED_CLK_SEL_R = crate::BitReader;
11#[doc = "Field `LOWSPEED_CLK_SEL` writer - "]
12pub type LOWSPEED_CLK_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `FAST_CLK_RTC_SEL` reader - "]
14pub type FAST_CLK_RTC_SEL_R = crate::BitReader;
15#[doc = "Field `FAST_CLK_RTC_SEL` writer - "]
16pub type FAST_CLK_RTC_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
17impl R {
18    #[doc = "Bits 0:1"]
19    #[inline(always)]
20    pub fn cpuperiod_sel(&self) -> CPUPERIOD_SEL_R {
21        CPUPERIOD_SEL_R::new((self.bits & 3) as u8)
22    }
23    #[doc = "Bit 2"]
24    #[inline(always)]
25    pub fn lowspeed_clk_sel(&self) -> LOWSPEED_CLK_SEL_R {
26        LOWSPEED_CLK_SEL_R::new(((self.bits >> 2) & 1) != 0)
27    }
28    #[doc = "Bit 3"]
29    #[inline(always)]
30    pub fn fast_clk_rtc_sel(&self) -> FAST_CLK_RTC_SEL_R {
31        FAST_CLK_RTC_SEL_R::new(((self.bits >> 3) & 1) != 0)
32    }
33}
34#[cfg(feature = "impl-register-debug")]
35impl core::fmt::Debug for R {
36    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
37        f.debug_struct("CPU_PER_CONF")
38            .field("cpuperiod_sel", &self.cpuperiod_sel())
39            .field("lowspeed_clk_sel", &self.lowspeed_clk_sel())
40            .field("fast_clk_rtc_sel", &self.fast_clk_rtc_sel())
41            .finish()
42    }
43}
44impl W {
45    #[doc = "Bits 0:1"]
46    #[inline(always)]
47    pub fn cpuperiod_sel(&mut self) -> CPUPERIOD_SEL_W<CPU_PER_CONF_SPEC> {
48        CPUPERIOD_SEL_W::new(self, 0)
49    }
50    #[doc = "Bit 2"]
51    #[inline(always)]
52    pub fn lowspeed_clk_sel(&mut self) -> LOWSPEED_CLK_SEL_W<CPU_PER_CONF_SPEC> {
53        LOWSPEED_CLK_SEL_W::new(self, 2)
54    }
55    #[doc = "Bit 3"]
56    #[inline(always)]
57    pub fn fast_clk_rtc_sel(&mut self) -> FAST_CLK_RTC_SEL_W<CPU_PER_CONF_SPEC> {
58        FAST_CLK_RTC_SEL_W::new(self, 3)
59    }
60}
61#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`cpu_per_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cpu_per_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
62pub struct CPU_PER_CONF_SPEC;
63impl crate::RegisterSpec for CPU_PER_CONF_SPEC {
64    type Ux = u32;
65}
66#[doc = "`read()` method returns [`cpu_per_conf::R`](R) reader structure"]
67impl crate::Readable for CPU_PER_CONF_SPEC {}
68#[doc = "`write(|w| ..)` method takes [`cpu_per_conf::W`](W) writer structure"]
69impl crate::Writable for CPU_PER_CONF_SPEC {
70    type Safety = crate::Unsafe;
71    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
72    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
73}
74#[doc = "`reset()` method sets CPU_PER_CONF to value 0"]
75impl crate::Resettable for CPU_PER_CONF_SPEC {
76    const RESET_VALUE: u32 = 0;
77}
esp32/dport/cpu_per_conf.rs

esp32/dport/
cpu_per_conf.rs
