Module ctrl2

Structs

CTRL2_SPEC

You can read this register and get ctrl2::R. You can reset, write, write_with_zero this register using ctrl2::W. You can also modify this register. See API.

Type Aliases

CK_OUT_HIGH_MODE_R

Field CK_OUT_HIGH_MODE reader - modify spi clock duty ratio when the value is lager than 8, the bits are combined with spi_clkcnt_N bits and spi_clkcnt_H bits.

CK_OUT_HIGH_MODE_W

Field CK_OUT_HIGH_MODE writer - modify spi clock duty ratio when the value is lager than 8, the bits are combined with spi_clkcnt_N bits and spi_clkcnt_H bits.

CK_OUT_LOW_MODE_R

Field CK_OUT_LOW_MODE reader - modify spi clock duty ratio when the value is lager than 8, the bits are combined with spi_clkcnt_N bits and spi_clkcnt_L bits.

CK_OUT_LOW_MODE_W

Field CK_OUT_LOW_MODE writer - modify spi clock duty ratio when the value is lager than 8, the bits are combined with spi_clkcnt_N bits and spi_clkcnt_L bits.

CS_DELAY_MODE_R

Field CS_DELAY_MODE reader - spi_cs signal is delayed by spi_clk . 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle

CS_DELAY_MODE_W

Field CS_DELAY_MODE writer - spi_cs signal is delayed by spi_clk . 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle

CS_DELAY_NUM_R

Field CS_DELAY_NUM reader - spi_cs signal is delayed by system clock cycles

CS_DELAY_NUM_W

Field CS_DELAY_NUM writer - spi_cs signal is delayed by system clock cycles

HOLD_TIME_R

Field HOLD_TIME reader - delay cycles of cs pin by spi clock, this bits combined with spi_cs_hold bit.

HOLD_TIME_W

Field HOLD_TIME writer - delay cycles of cs pin by spi clock, this bits combined with spi_cs_hold bit.

MISO_DELAY_MODE_R

Field MISO_DELAY_MODE reader - MISO signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle

MISO_DELAY_MODE_W

Field MISO_DELAY_MODE writer - MISO signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle

MISO_DELAY_NUM_R

Field MISO_DELAY_NUM reader - MISO signals are delayed by system clock cycles

MISO_DELAY_NUM_W

Field MISO_DELAY_NUM writer - MISO signals are delayed by system clock cycles

MOSI_DELAY_MODE_R

Field MOSI_DELAY_MODE reader - MOSI signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle

MOSI_DELAY_MODE_W

Field MOSI_DELAY_MODE writer - MOSI signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle

MOSI_DELAY_NUM_R

Field MOSI_DELAY_NUM reader - MOSI signals are delayed by system clock cycles

MOSI_DELAY_NUM_W

Field MOSI_DELAY_NUM writer - MOSI signals are delayed by system clock cycles

R

Register CTRL2 reader

SETUP_TIME_R

Field SETUP_TIME reader - (cycles-1) of ¡°prepare¡± phase by spi clock, this bits combined with spi_cs_setup bit.

SETUP_TIME_W

Field SETUP_TIME writer - (cycles-1) of ¡°prepare¡± phase by spi clock, this bits combined with spi_cs_setup bit.

W

Register CTRL2 writer