1#[doc = "Register `CTRL` reader"]
2pub type R = crate::R<CTRL_SPEC>;
3#[doc = "Register `CTRL` writer"]
4pub type W = crate::W<CTRL_SPEC>;
5#[doc = "Field `FCS_CRC_EN` reader - For SPI1 initialize crc32 module before writing encrypted data to flash. Active low."]
6pub type FCS_CRC_EN_R = crate::BitReader;
7#[doc = "Field `FCS_CRC_EN` writer - For SPI1 initialize crc32 module before writing encrypted data to flash. Active low."]
8pub type FCS_CRC_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `TX_CRC_EN` reader - For SPI1 enable crc32 when writing encrypted data to flash. 1: enable 0:disable"]
10pub type TX_CRC_EN_R = crate::BitReader;
11#[doc = "Field `TX_CRC_EN` writer - For SPI1 enable crc32 when writing encrypted data to flash. 1: enable 0:disable"]
12pub type TX_CRC_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `WAIT_FLASH_IDLE_EN` reader - wait flash idle when program flash or erase flash. 1: enable 0: disable."]
14pub type WAIT_FLASH_IDLE_EN_R = crate::BitReader;
15#[doc = "Field `WAIT_FLASH_IDLE_EN` writer - wait flash idle when program flash or erase flash. 1: enable 0: disable."]
16pub type WAIT_FLASH_IDLE_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `FASTRD_MODE` reader - This bit enable the bits: spi_fread_qio spi_fread_dio spi_fread_qout and spi_fread_dout. 1: enable 0: disable."]
18pub type FASTRD_MODE_R = crate::BitReader;
19#[doc = "Field `FASTRD_MODE` writer - This bit enable the bits: spi_fread_qio spi_fread_dio spi_fread_qout and spi_fread_dout. 1: enable 0: disable."]
20pub type FASTRD_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `FREAD_DUAL` reader - In the read operations read-data phase apply 2 signals. 1: enable 0: disable."]
22pub type FREAD_DUAL_R = crate::BitReader;
23#[doc = "Field `FREAD_DUAL` writer - In the read operations read-data phase apply 2 signals. 1: enable 0: disable."]
24pub type FREAD_DUAL_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `RESANDRES` reader - The Device ID is read out to SPI_RD_STATUS register, this bit combine with spi_flash_res bit. 1: enable 0: disable."]
26pub type RESANDRES_R = crate::BitReader;
27#[doc = "Field `RESANDRES` writer - The Device ID is read out to SPI_RD_STATUS register, this bit combine with spi_flash_res bit. 1: enable 0: disable."]
28pub type RESANDRES_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `FREAD_QUAD` reader - In the read operations read-data phase apply 4 signals. 1: enable 0: disable."]
30pub type FREAD_QUAD_R = crate::BitReader;
31#[doc = "Field `FREAD_QUAD` writer - In the read operations read-data phase apply 4 signals. 1: enable 0: disable."]
32pub type FREAD_QUAD_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `WP` reader - Write protect signal output when SPI is idle. 1: output high 0: output low."]
34pub type WP_R = crate::BitReader;
35#[doc = "Field `WP` writer - Write protect signal output when SPI is idle. 1: output high 0: output low."]
36pub type WP_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `WRSR_2B` reader - two bytes data will be written to status register when it is set. 1: enable 0: disable."]
38pub type WRSR_2B_R = crate::BitReader;
39#[doc = "Field `WRSR_2B` writer - two bytes data will be written to status register when it is set. 1: enable 0: disable."]
40pub type WRSR_2B_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `FREAD_DIO` reader - In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable."]
42pub type FREAD_DIO_R = crate::BitReader;
43#[doc = "Field `FREAD_DIO` writer - In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable."]
44pub type FREAD_DIO_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `FREAD_QIO` reader - In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable."]
46pub type FREAD_QIO_R = crate::BitReader;
47#[doc = "Field `FREAD_QIO` writer - In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable."]
48pub type FREAD_QIO_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `RD_BIT_ORDER` reader - In read-data (MISO) phase 1: LSB first 0: MSB first"]
50pub type RD_BIT_ORDER_R = crate::BitReader;
51#[doc = "Field `RD_BIT_ORDER` writer - In read-data (MISO) phase 1: LSB first 0: MSB first"]
52pub type RD_BIT_ORDER_W<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `WR_BIT_ORDER` reader - In command address write-data (MOSI) phases 1: LSB firs 0: MSB first"]
54pub type WR_BIT_ORDER_R = crate::BitReader;
55#[doc = "Field `WR_BIT_ORDER` writer - In command address write-data (MOSI) phases 1: LSB firs 0: MSB first"]
56pub type WR_BIT_ORDER_W<'a, REG> = crate::BitWriter<'a, REG>;
57impl R {
58 #[doc = "Bit 10 - For SPI1 initialize crc32 module before writing encrypted data to flash. Active low."]
59 #[inline(always)]
60 pub fn fcs_crc_en(&self) -> FCS_CRC_EN_R {
61 FCS_CRC_EN_R::new(((self.bits >> 10) & 1) != 0)
62 }
63 #[doc = "Bit 11 - For SPI1 enable crc32 when writing encrypted data to flash. 1: enable 0:disable"]
64 #[inline(always)]
65 pub fn tx_crc_en(&self) -> TX_CRC_EN_R {
66 TX_CRC_EN_R::new(((self.bits >> 11) & 1) != 0)
67 }
68 #[doc = "Bit 12 - wait flash idle when program flash or erase flash. 1: enable 0: disable."]
69 #[inline(always)]
70 pub fn wait_flash_idle_en(&self) -> WAIT_FLASH_IDLE_EN_R {
71 WAIT_FLASH_IDLE_EN_R::new(((self.bits >> 12) & 1) != 0)
72 }
73 #[doc = "Bit 13 - This bit enable the bits: spi_fread_qio spi_fread_dio spi_fread_qout and spi_fread_dout. 1: enable 0: disable."]
74 #[inline(always)]
75 pub fn fastrd_mode(&self) -> FASTRD_MODE_R {
76 FASTRD_MODE_R::new(((self.bits >> 13) & 1) != 0)
77 }
78 #[doc = "Bit 14 - In the read operations read-data phase apply 2 signals. 1: enable 0: disable."]
79 #[inline(always)]
80 pub fn fread_dual(&self) -> FREAD_DUAL_R {
81 FREAD_DUAL_R::new(((self.bits >> 14) & 1) != 0)
82 }
83 #[doc = "Bit 15 - The Device ID is read out to SPI_RD_STATUS register, this bit combine with spi_flash_res bit. 1: enable 0: disable."]
84 #[inline(always)]
85 pub fn resandres(&self) -> RESANDRES_R {
86 RESANDRES_R::new(((self.bits >> 15) & 1) != 0)
87 }
88 #[doc = "Bit 20 - In the read operations read-data phase apply 4 signals. 1: enable 0: disable."]
89 #[inline(always)]
90 pub fn fread_quad(&self) -> FREAD_QUAD_R {
91 FREAD_QUAD_R::new(((self.bits >> 20) & 1) != 0)
92 }
93 #[doc = "Bit 21 - Write protect signal output when SPI is idle. 1: output high 0: output low."]
94 #[inline(always)]
95 pub fn wp(&self) -> WP_R {
96 WP_R::new(((self.bits >> 21) & 1) != 0)
97 }
98 #[doc = "Bit 22 - two bytes data will be written to status register when it is set. 1: enable 0: disable."]
99 #[inline(always)]
100 pub fn wrsr_2b(&self) -> WRSR_2B_R {
101 WRSR_2B_R::new(((self.bits >> 22) & 1) != 0)
102 }
103 #[doc = "Bit 23 - In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable."]
104 #[inline(always)]
105 pub fn fread_dio(&self) -> FREAD_DIO_R {
106 FREAD_DIO_R::new(((self.bits >> 23) & 1) != 0)
107 }
108 #[doc = "Bit 24 - In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable."]
109 #[inline(always)]
110 pub fn fread_qio(&self) -> FREAD_QIO_R {
111 FREAD_QIO_R::new(((self.bits >> 24) & 1) != 0)
112 }
113 #[doc = "Bit 25 - In read-data (MISO) phase 1: LSB first 0: MSB first"]
114 #[inline(always)]
115 pub fn rd_bit_order(&self) -> RD_BIT_ORDER_R {
116 RD_BIT_ORDER_R::new(((self.bits >> 25) & 1) != 0)
117 }
118 #[doc = "Bit 26 - In command address write-data (MOSI) phases 1: LSB firs 0: MSB first"]
119 #[inline(always)]
120 pub fn wr_bit_order(&self) -> WR_BIT_ORDER_R {
121 WR_BIT_ORDER_R::new(((self.bits >> 26) & 1) != 0)
122 }
123}
124#[cfg(feature = "impl-register-debug")]
125impl core::fmt::Debug for R {
126 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
127 f.debug_struct("CTRL")
128 .field("fcs_crc_en", &self.fcs_crc_en())
129 .field("tx_crc_en", &self.tx_crc_en())
130 .field("wait_flash_idle_en", &self.wait_flash_idle_en())
131 .field("fastrd_mode", &self.fastrd_mode())
132 .field("fread_dual", &self.fread_dual())
133 .field("resandres", &self.resandres())
134 .field("fread_quad", &self.fread_quad())
135 .field("wp", &self.wp())
136 .field("wrsr_2b", &self.wrsr_2b())
137 .field("fread_dio", &self.fread_dio())
138 .field("fread_qio", &self.fread_qio())
139 .field("rd_bit_order", &self.rd_bit_order())
140 .field("wr_bit_order", &self.wr_bit_order())
141 .finish()
142 }
143}
144impl W {
145 #[doc = "Bit 10 - For SPI1 initialize crc32 module before writing encrypted data to flash. Active low."]
146 #[inline(always)]
147 pub fn fcs_crc_en(&mut self) -> FCS_CRC_EN_W<CTRL_SPEC> {
148 FCS_CRC_EN_W::new(self, 10)
149 }
150 #[doc = "Bit 11 - For SPI1 enable crc32 when writing encrypted data to flash. 1: enable 0:disable"]
151 #[inline(always)]
152 pub fn tx_crc_en(&mut self) -> TX_CRC_EN_W<CTRL_SPEC> {
153 TX_CRC_EN_W::new(self, 11)
154 }
155 #[doc = "Bit 12 - wait flash idle when program flash or erase flash. 1: enable 0: disable."]
156 #[inline(always)]
157 pub fn wait_flash_idle_en(&mut self) -> WAIT_FLASH_IDLE_EN_W<CTRL_SPEC> {
158 WAIT_FLASH_IDLE_EN_W::new(self, 12)
159 }
160 #[doc = "Bit 13 - This bit enable the bits: spi_fread_qio spi_fread_dio spi_fread_qout and spi_fread_dout. 1: enable 0: disable."]
161 #[inline(always)]
162 pub fn fastrd_mode(&mut self) -> FASTRD_MODE_W<CTRL_SPEC> {
163 FASTRD_MODE_W::new(self, 13)
164 }
165 #[doc = "Bit 14 - In the read operations read-data phase apply 2 signals. 1: enable 0: disable."]
166 #[inline(always)]
167 pub fn fread_dual(&mut self) -> FREAD_DUAL_W<CTRL_SPEC> {
168 FREAD_DUAL_W::new(self, 14)
169 }
170 #[doc = "Bit 15 - The Device ID is read out to SPI_RD_STATUS register, this bit combine with spi_flash_res bit. 1: enable 0: disable."]
171 #[inline(always)]
172 pub fn resandres(&mut self) -> RESANDRES_W<CTRL_SPEC> {
173 RESANDRES_W::new(self, 15)
174 }
175 #[doc = "Bit 20 - In the read operations read-data phase apply 4 signals. 1: enable 0: disable."]
176 #[inline(always)]
177 pub fn fread_quad(&mut self) -> FREAD_QUAD_W<CTRL_SPEC> {
178 FREAD_QUAD_W::new(self, 20)
179 }
180 #[doc = "Bit 21 - Write protect signal output when SPI is idle. 1: output high 0: output low."]
181 #[inline(always)]
182 pub fn wp(&mut self) -> WP_W<CTRL_SPEC> {
183 WP_W::new(self, 21)
184 }
185 #[doc = "Bit 22 - two bytes data will be written to status register when it is set. 1: enable 0: disable."]
186 #[inline(always)]
187 pub fn wrsr_2b(&mut self) -> WRSR_2B_W<CTRL_SPEC> {
188 WRSR_2B_W::new(self, 22)
189 }
190 #[doc = "Bit 23 - In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable."]
191 #[inline(always)]
192 pub fn fread_dio(&mut self) -> FREAD_DIO_W<CTRL_SPEC> {
193 FREAD_DIO_W::new(self, 23)
194 }
195 #[doc = "Bit 24 - In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable."]
196 #[inline(always)]
197 pub fn fread_qio(&mut self) -> FREAD_QIO_W<CTRL_SPEC> {
198 FREAD_QIO_W::new(self, 24)
199 }
200 #[doc = "Bit 25 - In read-data (MISO) phase 1: LSB first 0: MSB first"]
201 #[inline(always)]
202 pub fn rd_bit_order(&mut self) -> RD_BIT_ORDER_W<CTRL_SPEC> {
203 RD_BIT_ORDER_W::new(self, 25)
204 }
205 #[doc = "Bit 26 - In command address write-data (MOSI) phases 1: LSB firs 0: MSB first"]
206 #[inline(always)]
207 pub fn wr_bit_order(&mut self) -> WR_BIT_ORDER_W<CTRL_SPEC> {
208 WR_BIT_ORDER_W::new(self, 26)
209 }
210}
211#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
212pub struct CTRL_SPEC;
213impl crate::RegisterSpec for CTRL_SPEC {
214 type Ux = u32;
215}
216#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"]
217impl crate::Readable for CTRL_SPEC {}
218#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"]
219impl crate::Writable for CTRL_SPEC {
220 type Safety = crate::Unsafe;
221 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
222 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
223}
224#[doc = "`reset()` method sets CTRL to value 0x0020_a400"]
225impl crate::Resettable for CTRL_SPEC {
226 const RESET_VALUE: u32 = 0x0020_a400;
227}