esp32/slc/
_1int_ena1.rs

1#[doc = "Register `_1INT_ENA1` reader"]
2pub type R = crate::R<_1INT_ENA1_SPEC>;
3#[doc = "Register `_1INT_ENA1` writer"]
4pub type W = crate::W<_1INT_ENA1_SPEC>;
5#[doc = "Field `FRHOST_BIT8_INT_ENA1` reader - "]
6pub type FRHOST_BIT8_INT_ENA1_R = crate::BitReader;
7#[doc = "Field `FRHOST_BIT8_INT_ENA1` writer - "]
8pub type FRHOST_BIT8_INT_ENA1_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `FRHOST_BIT9_INT_ENA1` reader - "]
10pub type FRHOST_BIT9_INT_ENA1_R = crate::BitReader;
11#[doc = "Field `FRHOST_BIT9_INT_ENA1` writer - "]
12pub type FRHOST_BIT9_INT_ENA1_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `FRHOST_BIT10_INT_ENA1` reader - "]
14pub type FRHOST_BIT10_INT_ENA1_R = crate::BitReader;
15#[doc = "Field `FRHOST_BIT10_INT_ENA1` writer - "]
16pub type FRHOST_BIT10_INT_ENA1_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `FRHOST_BIT11_INT_ENA1` reader - "]
18pub type FRHOST_BIT11_INT_ENA1_R = crate::BitReader;
19#[doc = "Field `FRHOST_BIT11_INT_ENA1` writer - "]
20pub type FRHOST_BIT11_INT_ENA1_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `FRHOST_BIT12_INT_ENA1` reader - "]
22pub type FRHOST_BIT12_INT_ENA1_R = crate::BitReader;
23#[doc = "Field `FRHOST_BIT12_INT_ENA1` writer - "]
24pub type FRHOST_BIT12_INT_ENA1_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `FRHOST_BIT13_INT_ENA1` reader - "]
26pub type FRHOST_BIT13_INT_ENA1_R = crate::BitReader;
27#[doc = "Field `FRHOST_BIT13_INT_ENA1` writer - "]
28pub type FRHOST_BIT13_INT_ENA1_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `FRHOST_BIT14_INT_ENA1` reader - "]
30pub type FRHOST_BIT14_INT_ENA1_R = crate::BitReader;
31#[doc = "Field `FRHOST_BIT14_INT_ENA1` writer - "]
32pub type FRHOST_BIT14_INT_ENA1_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `FRHOST_BIT15_INT_ENA1` reader - "]
34pub type FRHOST_BIT15_INT_ENA1_R = crate::BitReader;
35#[doc = "Field `FRHOST_BIT15_INT_ENA1` writer - "]
36pub type FRHOST_BIT15_INT_ENA1_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `SLC1_RX_START_INT_ENA1` reader - "]
38pub type SLC1_RX_START_INT_ENA1_R = crate::BitReader;
39#[doc = "Field `SLC1_RX_START_INT_ENA1` writer - "]
40pub type SLC1_RX_START_INT_ENA1_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `SLC1_TX_START_INT_ENA1` reader - "]
42pub type SLC1_TX_START_INT_ENA1_R = crate::BitReader;
43#[doc = "Field `SLC1_TX_START_INT_ENA1` writer - "]
44pub type SLC1_TX_START_INT_ENA1_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `SLC1_RX_UDF_INT_ENA1` reader - "]
46pub type SLC1_RX_UDF_INT_ENA1_R = crate::BitReader;
47#[doc = "Field `SLC1_RX_UDF_INT_ENA1` writer - "]
48pub type SLC1_RX_UDF_INT_ENA1_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `SLC1_TX_OVF_INT_ENA1` reader - "]
50pub type SLC1_TX_OVF_INT_ENA1_R = crate::BitReader;
51#[doc = "Field `SLC1_TX_OVF_INT_ENA1` writer - "]
52pub type SLC1_TX_OVF_INT_ENA1_W<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `SLC1_TOKEN0_1TO0_INT_ENA1` reader - "]
54pub type SLC1_TOKEN0_1TO0_INT_ENA1_R = crate::BitReader;
55#[doc = "Field `SLC1_TOKEN0_1TO0_INT_ENA1` writer - "]
56pub type SLC1_TOKEN0_1TO0_INT_ENA1_W<'a, REG> = crate::BitWriter<'a, REG>;
57#[doc = "Field `SLC1_TOKEN1_1TO0_INT_ENA1` reader - "]
58pub type SLC1_TOKEN1_1TO0_INT_ENA1_R = crate::BitReader;
59#[doc = "Field `SLC1_TOKEN1_1TO0_INT_ENA1` writer - "]
60pub type SLC1_TOKEN1_1TO0_INT_ENA1_W<'a, REG> = crate::BitWriter<'a, REG>;
61#[doc = "Field `SLC1_TX_DONE_INT_ENA1` reader - "]
62pub type SLC1_TX_DONE_INT_ENA1_R = crate::BitReader;
63#[doc = "Field `SLC1_TX_DONE_INT_ENA1` writer - "]
64pub type SLC1_TX_DONE_INT_ENA1_W<'a, REG> = crate::BitWriter<'a, REG>;
65#[doc = "Field `SLC1_TX_SUC_EOF_INT_ENA1` reader - "]
66pub type SLC1_TX_SUC_EOF_INT_ENA1_R = crate::BitReader;
67#[doc = "Field `SLC1_TX_SUC_EOF_INT_ENA1` writer - "]
68pub type SLC1_TX_SUC_EOF_INT_ENA1_W<'a, REG> = crate::BitWriter<'a, REG>;
69#[doc = "Field `SLC1_RX_DONE_INT_ENA1` reader - "]
70pub type SLC1_RX_DONE_INT_ENA1_R = crate::BitReader;
71#[doc = "Field `SLC1_RX_DONE_INT_ENA1` writer - "]
72pub type SLC1_RX_DONE_INT_ENA1_W<'a, REG> = crate::BitWriter<'a, REG>;
73#[doc = "Field `SLC1_RX_EOF_INT_ENA1` reader - "]
74pub type SLC1_RX_EOF_INT_ENA1_R = crate::BitReader;
75#[doc = "Field `SLC1_RX_EOF_INT_ENA1` writer - "]
76pub type SLC1_RX_EOF_INT_ENA1_W<'a, REG> = crate::BitWriter<'a, REG>;
77#[doc = "Field `SLC1_TOHOST_INT_ENA1` reader - "]
78pub type SLC1_TOHOST_INT_ENA1_R = crate::BitReader;
79#[doc = "Field `SLC1_TOHOST_INT_ENA1` writer - "]
80pub type SLC1_TOHOST_INT_ENA1_W<'a, REG> = crate::BitWriter<'a, REG>;
81#[doc = "Field `SLC1_TX_DSCR_ERR_INT_ENA1` reader - "]
82pub type SLC1_TX_DSCR_ERR_INT_ENA1_R = crate::BitReader;
83#[doc = "Field `SLC1_TX_DSCR_ERR_INT_ENA1` writer - "]
84pub type SLC1_TX_DSCR_ERR_INT_ENA1_W<'a, REG> = crate::BitWriter<'a, REG>;
85#[doc = "Field `SLC1_RX_DSCR_ERR_INT_ENA1` reader - "]
86pub type SLC1_RX_DSCR_ERR_INT_ENA1_R = crate::BitReader;
87#[doc = "Field `SLC1_RX_DSCR_ERR_INT_ENA1` writer - "]
88pub type SLC1_RX_DSCR_ERR_INT_ENA1_W<'a, REG> = crate::BitWriter<'a, REG>;
89#[doc = "Field `SLC1_TX_DSCR_EMPTY_INT_ENA1` reader - "]
90pub type SLC1_TX_DSCR_EMPTY_INT_ENA1_R = crate::BitReader;
91#[doc = "Field `SLC1_TX_DSCR_EMPTY_INT_ENA1` writer - "]
92pub type SLC1_TX_DSCR_EMPTY_INT_ENA1_W<'a, REG> = crate::BitWriter<'a, REG>;
93#[doc = "Field `SLC1_HOST_RD_ACK_INT_ENA1` reader - "]
94pub type SLC1_HOST_RD_ACK_INT_ENA1_R = crate::BitReader;
95#[doc = "Field `SLC1_HOST_RD_ACK_INT_ENA1` writer - "]
96pub type SLC1_HOST_RD_ACK_INT_ENA1_W<'a, REG> = crate::BitWriter<'a, REG>;
97#[doc = "Field `SLC1_WR_RETRY_DONE_INT_ENA1` reader - "]
98pub type SLC1_WR_RETRY_DONE_INT_ENA1_R = crate::BitReader;
99#[doc = "Field `SLC1_WR_RETRY_DONE_INT_ENA1` writer - "]
100pub type SLC1_WR_RETRY_DONE_INT_ENA1_W<'a, REG> = crate::BitWriter<'a, REG>;
101#[doc = "Field `SLC1_TX_ERR_EOF_INT_ENA1` reader - "]
102pub type SLC1_TX_ERR_EOF_INT_ENA1_R = crate::BitReader;
103#[doc = "Field `SLC1_TX_ERR_EOF_INT_ENA1` writer - "]
104pub type SLC1_TX_ERR_EOF_INT_ENA1_W<'a, REG> = crate::BitWriter<'a, REG>;
105impl R {
106    #[doc = "Bit 0"]
107    #[inline(always)]
108    pub fn frhost_bit8_int_ena1(&self) -> FRHOST_BIT8_INT_ENA1_R {
109        FRHOST_BIT8_INT_ENA1_R::new((self.bits & 1) != 0)
110    }
111    #[doc = "Bit 1"]
112    #[inline(always)]
113    pub fn frhost_bit9_int_ena1(&self) -> FRHOST_BIT9_INT_ENA1_R {
114        FRHOST_BIT9_INT_ENA1_R::new(((self.bits >> 1) & 1) != 0)
115    }
116    #[doc = "Bit 2"]
117    #[inline(always)]
118    pub fn frhost_bit10_int_ena1(&self) -> FRHOST_BIT10_INT_ENA1_R {
119        FRHOST_BIT10_INT_ENA1_R::new(((self.bits >> 2) & 1) != 0)
120    }
121    #[doc = "Bit 3"]
122    #[inline(always)]
123    pub fn frhost_bit11_int_ena1(&self) -> FRHOST_BIT11_INT_ENA1_R {
124        FRHOST_BIT11_INT_ENA1_R::new(((self.bits >> 3) & 1) != 0)
125    }
126    #[doc = "Bit 4"]
127    #[inline(always)]
128    pub fn frhost_bit12_int_ena1(&self) -> FRHOST_BIT12_INT_ENA1_R {
129        FRHOST_BIT12_INT_ENA1_R::new(((self.bits >> 4) & 1) != 0)
130    }
131    #[doc = "Bit 5"]
132    #[inline(always)]
133    pub fn frhost_bit13_int_ena1(&self) -> FRHOST_BIT13_INT_ENA1_R {
134        FRHOST_BIT13_INT_ENA1_R::new(((self.bits >> 5) & 1) != 0)
135    }
136    #[doc = "Bit 6"]
137    #[inline(always)]
138    pub fn frhost_bit14_int_ena1(&self) -> FRHOST_BIT14_INT_ENA1_R {
139        FRHOST_BIT14_INT_ENA1_R::new(((self.bits >> 6) & 1) != 0)
140    }
141    #[doc = "Bit 7"]
142    #[inline(always)]
143    pub fn frhost_bit15_int_ena1(&self) -> FRHOST_BIT15_INT_ENA1_R {
144        FRHOST_BIT15_INT_ENA1_R::new(((self.bits >> 7) & 1) != 0)
145    }
146    #[doc = "Bit 8"]
147    #[inline(always)]
148    pub fn slc1_rx_start_int_ena1(&self) -> SLC1_RX_START_INT_ENA1_R {
149        SLC1_RX_START_INT_ENA1_R::new(((self.bits >> 8) & 1) != 0)
150    }
151    #[doc = "Bit 9"]
152    #[inline(always)]
153    pub fn slc1_tx_start_int_ena1(&self) -> SLC1_TX_START_INT_ENA1_R {
154        SLC1_TX_START_INT_ENA1_R::new(((self.bits >> 9) & 1) != 0)
155    }
156    #[doc = "Bit 10"]
157    #[inline(always)]
158    pub fn slc1_rx_udf_int_ena1(&self) -> SLC1_RX_UDF_INT_ENA1_R {
159        SLC1_RX_UDF_INT_ENA1_R::new(((self.bits >> 10) & 1) != 0)
160    }
161    #[doc = "Bit 11"]
162    #[inline(always)]
163    pub fn slc1_tx_ovf_int_ena1(&self) -> SLC1_TX_OVF_INT_ENA1_R {
164        SLC1_TX_OVF_INT_ENA1_R::new(((self.bits >> 11) & 1) != 0)
165    }
166    #[doc = "Bit 12"]
167    #[inline(always)]
168    pub fn slc1_token0_1to0_int_ena1(&self) -> SLC1_TOKEN0_1TO0_INT_ENA1_R {
169        SLC1_TOKEN0_1TO0_INT_ENA1_R::new(((self.bits >> 12) & 1) != 0)
170    }
171    #[doc = "Bit 13"]
172    #[inline(always)]
173    pub fn slc1_token1_1to0_int_ena1(&self) -> SLC1_TOKEN1_1TO0_INT_ENA1_R {
174        SLC1_TOKEN1_1TO0_INT_ENA1_R::new(((self.bits >> 13) & 1) != 0)
175    }
176    #[doc = "Bit 14"]
177    #[inline(always)]
178    pub fn slc1_tx_done_int_ena1(&self) -> SLC1_TX_DONE_INT_ENA1_R {
179        SLC1_TX_DONE_INT_ENA1_R::new(((self.bits >> 14) & 1) != 0)
180    }
181    #[doc = "Bit 15"]
182    #[inline(always)]
183    pub fn slc1_tx_suc_eof_int_ena1(&self) -> SLC1_TX_SUC_EOF_INT_ENA1_R {
184        SLC1_TX_SUC_EOF_INT_ENA1_R::new(((self.bits >> 15) & 1) != 0)
185    }
186    #[doc = "Bit 16"]
187    #[inline(always)]
188    pub fn slc1_rx_done_int_ena1(&self) -> SLC1_RX_DONE_INT_ENA1_R {
189        SLC1_RX_DONE_INT_ENA1_R::new(((self.bits >> 16) & 1) != 0)
190    }
191    #[doc = "Bit 17"]
192    #[inline(always)]
193    pub fn slc1_rx_eof_int_ena1(&self) -> SLC1_RX_EOF_INT_ENA1_R {
194        SLC1_RX_EOF_INT_ENA1_R::new(((self.bits >> 17) & 1) != 0)
195    }
196    #[doc = "Bit 18"]
197    #[inline(always)]
198    pub fn slc1_tohost_int_ena1(&self) -> SLC1_TOHOST_INT_ENA1_R {
199        SLC1_TOHOST_INT_ENA1_R::new(((self.bits >> 18) & 1) != 0)
200    }
201    #[doc = "Bit 19"]
202    #[inline(always)]
203    pub fn slc1_tx_dscr_err_int_ena1(&self) -> SLC1_TX_DSCR_ERR_INT_ENA1_R {
204        SLC1_TX_DSCR_ERR_INT_ENA1_R::new(((self.bits >> 19) & 1) != 0)
205    }
206    #[doc = "Bit 20"]
207    #[inline(always)]
208    pub fn slc1_rx_dscr_err_int_ena1(&self) -> SLC1_RX_DSCR_ERR_INT_ENA1_R {
209        SLC1_RX_DSCR_ERR_INT_ENA1_R::new(((self.bits >> 20) & 1) != 0)
210    }
211    #[doc = "Bit 21"]
212    #[inline(always)]
213    pub fn slc1_tx_dscr_empty_int_ena1(&self) -> SLC1_TX_DSCR_EMPTY_INT_ENA1_R {
214        SLC1_TX_DSCR_EMPTY_INT_ENA1_R::new(((self.bits >> 21) & 1) != 0)
215    }
216    #[doc = "Bit 22"]
217    #[inline(always)]
218    pub fn slc1_host_rd_ack_int_ena1(&self) -> SLC1_HOST_RD_ACK_INT_ENA1_R {
219        SLC1_HOST_RD_ACK_INT_ENA1_R::new(((self.bits >> 22) & 1) != 0)
220    }
221    #[doc = "Bit 23"]
222    #[inline(always)]
223    pub fn slc1_wr_retry_done_int_ena1(&self) -> SLC1_WR_RETRY_DONE_INT_ENA1_R {
224        SLC1_WR_RETRY_DONE_INT_ENA1_R::new(((self.bits >> 23) & 1) != 0)
225    }
226    #[doc = "Bit 24"]
227    #[inline(always)]
228    pub fn slc1_tx_err_eof_int_ena1(&self) -> SLC1_TX_ERR_EOF_INT_ENA1_R {
229        SLC1_TX_ERR_EOF_INT_ENA1_R::new(((self.bits >> 24) & 1) != 0)
230    }
231}
232#[cfg(feature = "impl-register-debug")]
233impl core::fmt::Debug for R {
234    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
235        f.debug_struct("_1INT_ENA1")
236            .field("frhost_bit8_int_ena1", &self.frhost_bit8_int_ena1())
237            .field("frhost_bit9_int_ena1", &self.frhost_bit9_int_ena1())
238            .field("frhost_bit10_int_ena1", &self.frhost_bit10_int_ena1())
239            .field("frhost_bit11_int_ena1", &self.frhost_bit11_int_ena1())
240            .field("frhost_bit12_int_ena1", &self.frhost_bit12_int_ena1())
241            .field("frhost_bit13_int_ena1", &self.frhost_bit13_int_ena1())
242            .field("frhost_bit14_int_ena1", &self.frhost_bit14_int_ena1())
243            .field("frhost_bit15_int_ena1", &self.frhost_bit15_int_ena1())
244            .field("slc1_rx_start_int_ena1", &self.slc1_rx_start_int_ena1())
245            .field("slc1_tx_start_int_ena1", &self.slc1_tx_start_int_ena1())
246            .field("slc1_rx_udf_int_ena1", &self.slc1_rx_udf_int_ena1())
247            .field("slc1_tx_ovf_int_ena1", &self.slc1_tx_ovf_int_ena1())
248            .field(
249                "slc1_token0_1to0_int_ena1",
250                &self.slc1_token0_1to0_int_ena1(),
251            )
252            .field(
253                "slc1_token1_1to0_int_ena1",
254                &self.slc1_token1_1to0_int_ena1(),
255            )
256            .field("slc1_tx_done_int_ena1", &self.slc1_tx_done_int_ena1())
257            .field("slc1_tx_suc_eof_int_ena1", &self.slc1_tx_suc_eof_int_ena1())
258            .field("slc1_rx_done_int_ena1", &self.slc1_rx_done_int_ena1())
259            .field("slc1_rx_eof_int_ena1", &self.slc1_rx_eof_int_ena1())
260            .field("slc1_tohost_int_ena1", &self.slc1_tohost_int_ena1())
261            .field(
262                "slc1_tx_dscr_err_int_ena1",
263                &self.slc1_tx_dscr_err_int_ena1(),
264            )
265            .field(
266                "slc1_rx_dscr_err_int_ena1",
267                &self.slc1_rx_dscr_err_int_ena1(),
268            )
269            .field(
270                "slc1_tx_dscr_empty_int_ena1",
271                &self.slc1_tx_dscr_empty_int_ena1(),
272            )
273            .field(
274                "slc1_host_rd_ack_int_ena1",
275                &self.slc1_host_rd_ack_int_ena1(),
276            )
277            .field(
278                "slc1_wr_retry_done_int_ena1",
279                &self.slc1_wr_retry_done_int_ena1(),
280            )
281            .field("slc1_tx_err_eof_int_ena1", &self.slc1_tx_err_eof_int_ena1())
282            .finish()
283    }
284}
285impl W {
286    #[doc = "Bit 0"]
287    #[inline(always)]
288    pub fn frhost_bit8_int_ena1(&mut self) -> FRHOST_BIT8_INT_ENA1_W<_1INT_ENA1_SPEC> {
289        FRHOST_BIT8_INT_ENA1_W::new(self, 0)
290    }
291    #[doc = "Bit 1"]
292    #[inline(always)]
293    pub fn frhost_bit9_int_ena1(&mut self) -> FRHOST_BIT9_INT_ENA1_W<_1INT_ENA1_SPEC> {
294        FRHOST_BIT9_INT_ENA1_W::new(self, 1)
295    }
296    #[doc = "Bit 2"]
297    #[inline(always)]
298    pub fn frhost_bit10_int_ena1(&mut self) -> FRHOST_BIT10_INT_ENA1_W<_1INT_ENA1_SPEC> {
299        FRHOST_BIT10_INT_ENA1_W::new(self, 2)
300    }
301    #[doc = "Bit 3"]
302    #[inline(always)]
303    pub fn frhost_bit11_int_ena1(&mut self) -> FRHOST_BIT11_INT_ENA1_W<_1INT_ENA1_SPEC> {
304        FRHOST_BIT11_INT_ENA1_W::new(self, 3)
305    }
306    #[doc = "Bit 4"]
307    #[inline(always)]
308    pub fn frhost_bit12_int_ena1(&mut self) -> FRHOST_BIT12_INT_ENA1_W<_1INT_ENA1_SPEC> {
309        FRHOST_BIT12_INT_ENA1_W::new(self, 4)
310    }
311    #[doc = "Bit 5"]
312    #[inline(always)]
313    pub fn frhost_bit13_int_ena1(&mut self) -> FRHOST_BIT13_INT_ENA1_W<_1INT_ENA1_SPEC> {
314        FRHOST_BIT13_INT_ENA1_W::new(self, 5)
315    }
316    #[doc = "Bit 6"]
317    #[inline(always)]
318    pub fn frhost_bit14_int_ena1(&mut self) -> FRHOST_BIT14_INT_ENA1_W<_1INT_ENA1_SPEC> {
319        FRHOST_BIT14_INT_ENA1_W::new(self, 6)
320    }
321    #[doc = "Bit 7"]
322    #[inline(always)]
323    pub fn frhost_bit15_int_ena1(&mut self) -> FRHOST_BIT15_INT_ENA1_W<_1INT_ENA1_SPEC> {
324        FRHOST_BIT15_INT_ENA1_W::new(self, 7)
325    }
326    #[doc = "Bit 8"]
327    #[inline(always)]
328    pub fn slc1_rx_start_int_ena1(&mut self) -> SLC1_RX_START_INT_ENA1_W<_1INT_ENA1_SPEC> {
329        SLC1_RX_START_INT_ENA1_W::new(self, 8)
330    }
331    #[doc = "Bit 9"]
332    #[inline(always)]
333    pub fn slc1_tx_start_int_ena1(&mut self) -> SLC1_TX_START_INT_ENA1_W<_1INT_ENA1_SPEC> {
334        SLC1_TX_START_INT_ENA1_W::new(self, 9)
335    }
336    #[doc = "Bit 10"]
337    #[inline(always)]
338    pub fn slc1_rx_udf_int_ena1(&mut self) -> SLC1_RX_UDF_INT_ENA1_W<_1INT_ENA1_SPEC> {
339        SLC1_RX_UDF_INT_ENA1_W::new(self, 10)
340    }
341    #[doc = "Bit 11"]
342    #[inline(always)]
343    pub fn slc1_tx_ovf_int_ena1(&mut self) -> SLC1_TX_OVF_INT_ENA1_W<_1INT_ENA1_SPEC> {
344        SLC1_TX_OVF_INT_ENA1_W::new(self, 11)
345    }
346    #[doc = "Bit 12"]
347    #[inline(always)]
348    pub fn slc1_token0_1to0_int_ena1(&mut self) -> SLC1_TOKEN0_1TO0_INT_ENA1_W<_1INT_ENA1_SPEC> {
349        SLC1_TOKEN0_1TO0_INT_ENA1_W::new(self, 12)
350    }
351    #[doc = "Bit 13"]
352    #[inline(always)]
353    pub fn slc1_token1_1to0_int_ena1(&mut self) -> SLC1_TOKEN1_1TO0_INT_ENA1_W<_1INT_ENA1_SPEC> {
354        SLC1_TOKEN1_1TO0_INT_ENA1_W::new(self, 13)
355    }
356    #[doc = "Bit 14"]
357    #[inline(always)]
358    pub fn slc1_tx_done_int_ena1(&mut self) -> SLC1_TX_DONE_INT_ENA1_W<_1INT_ENA1_SPEC> {
359        SLC1_TX_DONE_INT_ENA1_W::new(self, 14)
360    }
361    #[doc = "Bit 15"]
362    #[inline(always)]
363    pub fn slc1_tx_suc_eof_int_ena1(&mut self) -> SLC1_TX_SUC_EOF_INT_ENA1_W<_1INT_ENA1_SPEC> {
364        SLC1_TX_SUC_EOF_INT_ENA1_W::new(self, 15)
365    }
366    #[doc = "Bit 16"]
367    #[inline(always)]
368    pub fn slc1_rx_done_int_ena1(&mut self) -> SLC1_RX_DONE_INT_ENA1_W<_1INT_ENA1_SPEC> {
369        SLC1_RX_DONE_INT_ENA1_W::new(self, 16)
370    }
371    #[doc = "Bit 17"]
372    #[inline(always)]
373    pub fn slc1_rx_eof_int_ena1(&mut self) -> SLC1_RX_EOF_INT_ENA1_W<_1INT_ENA1_SPEC> {
374        SLC1_RX_EOF_INT_ENA1_W::new(self, 17)
375    }
376    #[doc = "Bit 18"]
377    #[inline(always)]
378    pub fn slc1_tohost_int_ena1(&mut self) -> SLC1_TOHOST_INT_ENA1_W<_1INT_ENA1_SPEC> {
379        SLC1_TOHOST_INT_ENA1_W::new(self, 18)
380    }
381    #[doc = "Bit 19"]
382    #[inline(always)]
383    pub fn slc1_tx_dscr_err_int_ena1(&mut self) -> SLC1_TX_DSCR_ERR_INT_ENA1_W<_1INT_ENA1_SPEC> {
384        SLC1_TX_DSCR_ERR_INT_ENA1_W::new(self, 19)
385    }
386    #[doc = "Bit 20"]
387    #[inline(always)]
388    pub fn slc1_rx_dscr_err_int_ena1(&mut self) -> SLC1_RX_DSCR_ERR_INT_ENA1_W<_1INT_ENA1_SPEC> {
389        SLC1_RX_DSCR_ERR_INT_ENA1_W::new(self, 20)
390    }
391    #[doc = "Bit 21"]
392    #[inline(always)]
393    pub fn slc1_tx_dscr_empty_int_ena1(
394        &mut self,
395    ) -> SLC1_TX_DSCR_EMPTY_INT_ENA1_W<_1INT_ENA1_SPEC> {
396        SLC1_TX_DSCR_EMPTY_INT_ENA1_W::new(self, 21)
397    }
398    #[doc = "Bit 22"]
399    #[inline(always)]
400    pub fn slc1_host_rd_ack_int_ena1(&mut self) -> SLC1_HOST_RD_ACK_INT_ENA1_W<_1INT_ENA1_SPEC> {
401        SLC1_HOST_RD_ACK_INT_ENA1_W::new(self, 22)
402    }
403    #[doc = "Bit 23"]
404    #[inline(always)]
405    pub fn slc1_wr_retry_done_int_ena1(
406        &mut self,
407    ) -> SLC1_WR_RETRY_DONE_INT_ENA1_W<_1INT_ENA1_SPEC> {
408        SLC1_WR_RETRY_DONE_INT_ENA1_W::new(self, 23)
409    }
410    #[doc = "Bit 24"]
411    #[inline(always)]
412    pub fn slc1_tx_err_eof_int_ena1(&mut self) -> SLC1_TX_ERR_EOF_INT_ENA1_W<_1INT_ENA1_SPEC> {
413        SLC1_TX_ERR_EOF_INT_ENA1_W::new(self, 24)
414    }
415}
416#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`_1int_ena1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`_1int_ena1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
417pub struct _1INT_ENA1_SPEC;
418impl crate::RegisterSpec for _1INT_ENA1_SPEC {
419    type Ux = u32;
420}
421#[doc = "`read()` method returns [`_1int_ena1::R`](R) reader structure"]
422impl crate::Readable for _1INT_ENA1_SPEC {}
423#[doc = "`write(|w| ..)` method takes [`_1int_ena1::W`](W) writer structure"]
424impl crate::Writable for _1INT_ENA1_SPEC {
425    type Safety = crate::Unsafe;
426    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
427    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
428}
429#[doc = "`reset()` method sets _1INT_ENA1 to value 0"]
430impl crate::Resettable for _1INT_ENA1_SPEC {
431    const RESET_VALUE: u32 = 0;
432}
esp32/slc/_1int_ena1.rs

esp32/slc/
_1int_ena1.rs
