1#[doc = "Register `_0INT_CLR` writer"]
2pub type W = crate::W<_0INT_CLR_SPEC>;
3#[doc = "Field `FRHOST_BIT0_INT_CLR` writer - "]
4pub type FRHOST_BIT0_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
5#[doc = "Field `FRHOST_BIT1_INT_CLR` writer - "]
6pub type FRHOST_BIT1_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
7#[doc = "Field `FRHOST_BIT2_INT_CLR` writer - "]
8pub type FRHOST_BIT2_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `FRHOST_BIT3_INT_CLR` writer - "]
10pub type FRHOST_BIT3_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
11#[doc = "Field `FRHOST_BIT4_INT_CLR` writer - "]
12pub type FRHOST_BIT4_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `FRHOST_BIT5_INT_CLR` writer - "]
14pub type FRHOST_BIT5_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
15#[doc = "Field `FRHOST_BIT6_INT_CLR` writer - "]
16pub type FRHOST_BIT6_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `FRHOST_BIT7_INT_CLR` writer - "]
18pub type FRHOST_BIT7_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
19#[doc = "Field `SLC0_RX_START_INT_CLR` writer - "]
20pub type SLC0_RX_START_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `SLC0_TX_START_INT_CLR` writer - "]
22pub type SLC0_TX_START_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
23#[doc = "Field `SLC0_RX_UDF_INT_CLR` writer - "]
24pub type SLC0_RX_UDF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `SLC0_TX_OVF_INT_CLR` writer - "]
26pub type SLC0_TX_OVF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
27#[doc = "Field `SLC0_TOKEN0_1TO0_INT_CLR` writer - "]
28pub type SLC0_TOKEN0_1TO0_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `SLC0_TOKEN1_1TO0_INT_CLR` writer - "]
30pub type SLC0_TOKEN1_1TO0_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
31#[doc = "Field `SLC0_TX_DONE_INT_CLR` writer - "]
32pub type SLC0_TX_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `SLC0_TX_SUC_EOF_INT_CLR` writer - "]
34pub type SLC0_TX_SUC_EOF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
35#[doc = "Field `SLC0_RX_DONE_INT_CLR` writer - "]
36pub type SLC0_RX_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `SLC0_RX_EOF_INT_CLR` writer - "]
38pub type SLC0_RX_EOF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
39#[doc = "Field `SLC0_TOHOST_INT_CLR` writer - "]
40pub type SLC0_TOHOST_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `SLC0_TX_DSCR_ERR_INT_CLR` writer - "]
42pub type SLC0_TX_DSCR_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
43#[doc = "Field `SLC0_RX_DSCR_ERR_INT_CLR` writer - "]
44pub type SLC0_RX_DSCR_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `SLC0_TX_DSCR_EMPTY_INT_CLR` writer - "]
46pub type SLC0_TX_DSCR_EMPTY_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
47#[doc = "Field `SLC0_HOST_RD_ACK_INT_CLR` writer - "]
48pub type SLC0_HOST_RD_ACK_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `SLC0_WR_RETRY_DONE_INT_CLR` writer - "]
50pub type SLC0_WR_RETRY_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
51#[doc = "Field `SLC0_TX_ERR_EOF_INT_CLR` writer - "]
52pub type SLC0_TX_ERR_EOF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `CMD_DTC_INT_CLR` writer - "]
54pub type CMD_DTC_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
55#[doc = "Field `SLC0_RX_QUICK_EOF_INT_CLR` writer - "]
56pub type SLC0_RX_QUICK_EOF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
57#[cfg(feature = "impl-register-debug")]
58impl core::fmt::Debug for crate::generic::Reg<_0INT_CLR_SPEC> {
59 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
60 write!(f, "(not readable)")
61 }
62}
63impl W {
64 #[doc = "Bit 0"]
65 #[inline(always)]
66 pub fn frhost_bit0_int_clr(&mut self) -> FRHOST_BIT0_INT_CLR_W<_0INT_CLR_SPEC> {
67 FRHOST_BIT0_INT_CLR_W::new(self, 0)
68 }
69 #[doc = "Bit 1"]
70 #[inline(always)]
71 pub fn frhost_bit1_int_clr(&mut self) -> FRHOST_BIT1_INT_CLR_W<_0INT_CLR_SPEC> {
72 FRHOST_BIT1_INT_CLR_W::new(self, 1)
73 }
74 #[doc = "Bit 2"]
75 #[inline(always)]
76 pub fn frhost_bit2_int_clr(&mut self) -> FRHOST_BIT2_INT_CLR_W<_0INT_CLR_SPEC> {
77 FRHOST_BIT2_INT_CLR_W::new(self, 2)
78 }
79 #[doc = "Bit 3"]
80 #[inline(always)]
81 pub fn frhost_bit3_int_clr(&mut self) -> FRHOST_BIT3_INT_CLR_W<_0INT_CLR_SPEC> {
82 FRHOST_BIT3_INT_CLR_W::new(self, 3)
83 }
84 #[doc = "Bit 4"]
85 #[inline(always)]
86 pub fn frhost_bit4_int_clr(&mut self) -> FRHOST_BIT4_INT_CLR_W<_0INT_CLR_SPEC> {
87 FRHOST_BIT4_INT_CLR_W::new(self, 4)
88 }
89 #[doc = "Bit 5"]
90 #[inline(always)]
91 pub fn frhost_bit5_int_clr(&mut self) -> FRHOST_BIT5_INT_CLR_W<_0INT_CLR_SPEC> {
92 FRHOST_BIT5_INT_CLR_W::new(self, 5)
93 }
94 #[doc = "Bit 6"]
95 #[inline(always)]
96 pub fn frhost_bit6_int_clr(&mut self) -> FRHOST_BIT6_INT_CLR_W<_0INT_CLR_SPEC> {
97 FRHOST_BIT6_INT_CLR_W::new(self, 6)
98 }
99 #[doc = "Bit 7"]
100 #[inline(always)]
101 pub fn frhost_bit7_int_clr(&mut self) -> FRHOST_BIT7_INT_CLR_W<_0INT_CLR_SPEC> {
102 FRHOST_BIT7_INT_CLR_W::new(self, 7)
103 }
104 #[doc = "Bit 8"]
105 #[inline(always)]
106 pub fn slc0_rx_start_int_clr(&mut self) -> SLC0_RX_START_INT_CLR_W<_0INT_CLR_SPEC> {
107 SLC0_RX_START_INT_CLR_W::new(self, 8)
108 }
109 #[doc = "Bit 9"]
110 #[inline(always)]
111 pub fn slc0_tx_start_int_clr(&mut self) -> SLC0_TX_START_INT_CLR_W<_0INT_CLR_SPEC> {
112 SLC0_TX_START_INT_CLR_W::new(self, 9)
113 }
114 #[doc = "Bit 10"]
115 #[inline(always)]
116 pub fn slc0_rx_udf_int_clr(&mut self) -> SLC0_RX_UDF_INT_CLR_W<_0INT_CLR_SPEC> {
117 SLC0_RX_UDF_INT_CLR_W::new(self, 10)
118 }
119 #[doc = "Bit 11"]
120 #[inline(always)]
121 pub fn slc0_tx_ovf_int_clr(&mut self) -> SLC0_TX_OVF_INT_CLR_W<_0INT_CLR_SPEC> {
122 SLC0_TX_OVF_INT_CLR_W::new(self, 11)
123 }
124 #[doc = "Bit 12"]
125 #[inline(always)]
126 pub fn slc0_token0_1to0_int_clr(&mut self) -> SLC0_TOKEN0_1TO0_INT_CLR_W<_0INT_CLR_SPEC> {
127 SLC0_TOKEN0_1TO0_INT_CLR_W::new(self, 12)
128 }
129 #[doc = "Bit 13"]
130 #[inline(always)]
131 pub fn slc0_token1_1to0_int_clr(&mut self) -> SLC0_TOKEN1_1TO0_INT_CLR_W<_0INT_CLR_SPEC> {
132 SLC0_TOKEN1_1TO0_INT_CLR_W::new(self, 13)
133 }
134 #[doc = "Bit 14"]
135 #[inline(always)]
136 pub fn slc0_tx_done_int_clr(&mut self) -> SLC0_TX_DONE_INT_CLR_W<_0INT_CLR_SPEC> {
137 SLC0_TX_DONE_INT_CLR_W::new(self, 14)
138 }
139 #[doc = "Bit 15"]
140 #[inline(always)]
141 pub fn slc0_tx_suc_eof_int_clr(&mut self) -> SLC0_TX_SUC_EOF_INT_CLR_W<_0INT_CLR_SPEC> {
142 SLC0_TX_SUC_EOF_INT_CLR_W::new(self, 15)
143 }
144 #[doc = "Bit 16"]
145 #[inline(always)]
146 pub fn slc0_rx_done_int_clr(&mut self) -> SLC0_RX_DONE_INT_CLR_W<_0INT_CLR_SPEC> {
147 SLC0_RX_DONE_INT_CLR_W::new(self, 16)
148 }
149 #[doc = "Bit 17"]
150 #[inline(always)]
151 pub fn slc0_rx_eof_int_clr(&mut self) -> SLC0_RX_EOF_INT_CLR_W<_0INT_CLR_SPEC> {
152 SLC0_RX_EOF_INT_CLR_W::new(self, 17)
153 }
154 #[doc = "Bit 18"]
155 #[inline(always)]
156 pub fn slc0_tohost_int_clr(&mut self) -> SLC0_TOHOST_INT_CLR_W<_0INT_CLR_SPEC> {
157 SLC0_TOHOST_INT_CLR_W::new(self, 18)
158 }
159 #[doc = "Bit 19"]
160 #[inline(always)]
161 pub fn slc0_tx_dscr_err_int_clr(&mut self) -> SLC0_TX_DSCR_ERR_INT_CLR_W<_0INT_CLR_SPEC> {
162 SLC0_TX_DSCR_ERR_INT_CLR_W::new(self, 19)
163 }
164 #[doc = "Bit 20"]
165 #[inline(always)]
166 pub fn slc0_rx_dscr_err_int_clr(&mut self) -> SLC0_RX_DSCR_ERR_INT_CLR_W<_0INT_CLR_SPEC> {
167 SLC0_RX_DSCR_ERR_INT_CLR_W::new(self, 20)
168 }
169 #[doc = "Bit 21"]
170 #[inline(always)]
171 pub fn slc0_tx_dscr_empty_int_clr(&mut self) -> SLC0_TX_DSCR_EMPTY_INT_CLR_W<_0INT_CLR_SPEC> {
172 SLC0_TX_DSCR_EMPTY_INT_CLR_W::new(self, 21)
173 }
174 #[doc = "Bit 22"]
175 #[inline(always)]
176 pub fn slc0_host_rd_ack_int_clr(&mut self) -> SLC0_HOST_RD_ACK_INT_CLR_W<_0INT_CLR_SPEC> {
177 SLC0_HOST_RD_ACK_INT_CLR_W::new(self, 22)
178 }
179 #[doc = "Bit 23"]
180 #[inline(always)]
181 pub fn slc0_wr_retry_done_int_clr(&mut self) -> SLC0_WR_RETRY_DONE_INT_CLR_W<_0INT_CLR_SPEC> {
182 SLC0_WR_RETRY_DONE_INT_CLR_W::new(self, 23)
183 }
184 #[doc = "Bit 24"]
185 #[inline(always)]
186 pub fn slc0_tx_err_eof_int_clr(&mut self) -> SLC0_TX_ERR_EOF_INT_CLR_W<_0INT_CLR_SPEC> {
187 SLC0_TX_ERR_EOF_INT_CLR_W::new(self, 24)
188 }
189 #[doc = "Bit 25"]
190 #[inline(always)]
191 pub fn cmd_dtc_int_clr(&mut self) -> CMD_DTC_INT_CLR_W<_0INT_CLR_SPEC> {
192 CMD_DTC_INT_CLR_W::new(self, 25)
193 }
194 #[doc = "Bit 26"]
195 #[inline(always)]
196 pub fn slc0_rx_quick_eof_int_clr(&mut self) -> SLC0_RX_QUICK_EOF_INT_CLR_W<_0INT_CLR_SPEC> {
197 SLC0_RX_QUICK_EOF_INT_CLR_W::new(self, 26)
198 }
199}
200#[doc = "\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`_0int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
201pub struct _0INT_CLR_SPEC;
202impl crate::RegisterSpec for _0INT_CLR_SPEC {
203 type Ux = u32;
204}
205#[doc = "`write(|w| ..)` method takes [`_0int_clr::W`](W) writer structure"]
206impl crate::Writable for _0INT_CLR_SPEC {
207 type Safety = crate::Unsafe;
208 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
209 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
210}
211#[doc = "`reset()` method sets _0INT_CLR to value 0"]
212impl crate::Resettable for _0INT_CLR_SPEC {
213 const RESET_VALUE: u32 = 0;
214}