esp32/mcpwm0/
timer_synci_cfg.rs

1#[doc = "Register `TIMER_SYNCI_CFG` reader"]
2pub type R = crate::R<TIMER_SYNCI_CFG_SPEC>;
3#[doc = "Register `TIMER_SYNCI_CFG` writer"]
4pub type W = crate::W<TIMER_SYNCI_CFG_SPEC>;
5#[doc = "Field `TIMER0_SYNCISEL` reader - "]
6pub type TIMER0_SYNCISEL_R = crate::FieldReader;
7#[doc = "Field `TIMER0_SYNCISEL` writer - "]
8pub type TIMER0_SYNCISEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
9#[doc = "Field `TIMER1_SYNCISEL` reader - "]
10pub type TIMER1_SYNCISEL_R = crate::FieldReader;
11#[doc = "Field `TIMER1_SYNCISEL` writer - "]
12pub type TIMER1_SYNCISEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
13#[doc = "Field `TIMER2_SYNCISEL` reader - "]
14pub type TIMER2_SYNCISEL_R = crate::FieldReader;
15#[doc = "Field `TIMER2_SYNCISEL` writer - "]
16pub type TIMER2_SYNCISEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
17#[doc = "Field `EXTERNAL_SYNCI0_INVERT` reader - "]
18pub type EXTERNAL_SYNCI0_INVERT_R = crate::BitReader;
19#[doc = "Field `EXTERNAL_SYNCI0_INVERT` writer - "]
20pub type EXTERNAL_SYNCI0_INVERT_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `EXTERNAL_SYNCI1_INVERT` reader - "]
22pub type EXTERNAL_SYNCI1_INVERT_R = crate::BitReader;
23#[doc = "Field `EXTERNAL_SYNCI1_INVERT` writer - "]
24pub type EXTERNAL_SYNCI1_INVERT_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `EXTERNAL_SYNCI2_INVERT` reader - "]
26pub type EXTERNAL_SYNCI2_INVERT_R = crate::BitReader;
27#[doc = "Field `EXTERNAL_SYNCI2_INVERT` writer - "]
28pub type EXTERNAL_SYNCI2_INVERT_W<'a, REG> = crate::BitWriter<'a, REG>;
29impl R {
30    #[doc = "Bits 0:2"]
31    #[inline(always)]
32    pub fn timer0_syncisel(&self) -> TIMER0_SYNCISEL_R {
33        TIMER0_SYNCISEL_R::new((self.bits & 7) as u8)
34    }
35    #[doc = "Bits 3:5"]
36    #[inline(always)]
37    pub fn timer1_syncisel(&self) -> TIMER1_SYNCISEL_R {
38        TIMER1_SYNCISEL_R::new(((self.bits >> 3) & 7) as u8)
39    }
40    #[doc = "Bits 6:8"]
41    #[inline(always)]
42    pub fn timer2_syncisel(&self) -> TIMER2_SYNCISEL_R {
43        TIMER2_SYNCISEL_R::new(((self.bits >> 6) & 7) as u8)
44    }
45    #[doc = "Bit 9"]
46    #[inline(always)]
47    pub fn external_synci0_invert(&self) -> EXTERNAL_SYNCI0_INVERT_R {
48        EXTERNAL_SYNCI0_INVERT_R::new(((self.bits >> 9) & 1) != 0)
49    }
50    #[doc = "Bit 10"]
51    #[inline(always)]
52    pub fn external_synci1_invert(&self) -> EXTERNAL_SYNCI1_INVERT_R {
53        EXTERNAL_SYNCI1_INVERT_R::new(((self.bits >> 10) & 1) != 0)
54    }
55    #[doc = "Bit 11"]
56    #[inline(always)]
57    pub fn external_synci2_invert(&self) -> EXTERNAL_SYNCI2_INVERT_R {
58        EXTERNAL_SYNCI2_INVERT_R::new(((self.bits >> 11) & 1) != 0)
59    }
60}
61#[cfg(feature = "impl-register-debug")]
62impl core::fmt::Debug for R {
63    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
64        f.debug_struct("TIMER_SYNCI_CFG")
65            .field("timer0_syncisel", &self.timer0_syncisel())
66            .field("timer1_syncisel", &self.timer1_syncisel())
67            .field("timer2_syncisel", &self.timer2_syncisel())
68            .field("external_synci0_invert", &self.external_synci0_invert())
69            .field("external_synci1_invert", &self.external_synci1_invert())
70            .field("external_synci2_invert", &self.external_synci2_invert())
71            .finish()
72    }
73}
74impl W {
75    #[doc = "Bits 0:2"]
76    #[inline(always)]
77    pub fn timer0_syncisel(&mut self) -> TIMER0_SYNCISEL_W<TIMER_SYNCI_CFG_SPEC> {
78        TIMER0_SYNCISEL_W::new(self, 0)
79    }
80    #[doc = "Bits 3:5"]
81    #[inline(always)]
82    pub fn timer1_syncisel(&mut self) -> TIMER1_SYNCISEL_W<TIMER_SYNCI_CFG_SPEC> {
83        TIMER1_SYNCISEL_W::new(self, 3)
84    }
85    #[doc = "Bits 6:8"]
86    #[inline(always)]
87    pub fn timer2_syncisel(&mut self) -> TIMER2_SYNCISEL_W<TIMER_SYNCI_CFG_SPEC> {
88        TIMER2_SYNCISEL_W::new(self, 6)
89    }
90    #[doc = "Bit 9"]
91    #[inline(always)]
92    pub fn external_synci0_invert(&mut self) -> EXTERNAL_SYNCI0_INVERT_W<TIMER_SYNCI_CFG_SPEC> {
93        EXTERNAL_SYNCI0_INVERT_W::new(self, 9)
94    }
95    #[doc = "Bit 10"]
96    #[inline(always)]
97    pub fn external_synci1_invert(&mut self) -> EXTERNAL_SYNCI1_INVERT_W<TIMER_SYNCI_CFG_SPEC> {
98        EXTERNAL_SYNCI1_INVERT_W::new(self, 10)
99    }
100    #[doc = "Bit 11"]
101    #[inline(always)]
102    pub fn external_synci2_invert(&mut self) -> EXTERNAL_SYNCI2_INVERT_W<TIMER_SYNCI_CFG_SPEC> {
103        EXTERNAL_SYNCI2_INVERT_W::new(self, 11)
104    }
105}
106#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`timer_synci_cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer_synci_cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
107pub struct TIMER_SYNCI_CFG_SPEC;
108impl crate::RegisterSpec for TIMER_SYNCI_CFG_SPEC {
109    type Ux = u32;
110}
111#[doc = "`read()` method returns [`timer_synci_cfg::R`](R) reader structure"]
112impl crate::Readable for TIMER_SYNCI_CFG_SPEC {}
113#[doc = "`write(|w| ..)` method takes [`timer_synci_cfg::W`](W) writer structure"]
114impl crate::Writable for TIMER_SYNCI_CFG_SPEC {
115    type Safety = crate::Unsafe;
116    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
117    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
118}
119#[doc = "`reset()` method sets TIMER_SYNCI_CFG to value 0"]
120impl crate::Resettable for TIMER_SYNCI_CFG_SPEC {
121    const RESET_VALUE: u32 = 0;
122}
esp32/mcpwm0/timer_synci_cfg.rs

esp32/mcpwm0/
timer_synci_cfg.rs
