esp32/efuse/
blk0_wdata3.rs

1#[doc = "Register `BLK0_WDATA3` reader"]
2pub type R = crate::R<BLK0_WDATA3_SPEC>;
3#[doc = "Register `BLK0_WDATA3` writer"]
4pub type W = crate::W<BLK0_WDATA3_SPEC>;
5#[doc = "Field `DISABLE_APP_CPU` reader - "]
6pub type DISABLE_APP_CPU_R = crate::BitReader;
7#[doc = "Field `DISABLE_BT` reader - "]
8pub type DISABLE_BT_R = crate::BitReader;
9#[doc = "Field `CHIP_PACKAGE_4BIT` reader - "]
10pub type CHIP_PACKAGE_4BIT_R = crate::BitReader;
11#[doc = "Field `DIS_CACHE` reader - "]
12pub type DIS_CACHE_R = crate::BitReader;
13#[doc = "Field `SPI_PAD_CONFIG_HD` reader - "]
14pub type SPI_PAD_CONFIG_HD_R = crate::FieldReader;
15#[doc = "Field `CHIP_PACKAGE` reader - "]
16pub type CHIP_PACKAGE_R = crate::FieldReader;
17#[doc = "Field `CHIP_PACKAGE` writer - "]
18pub type CHIP_PACKAGE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
19#[doc = "Field `CHIP_CPU_FREQ_LOW` reader - "]
20pub type CHIP_CPU_FREQ_LOW_R = crate::BitReader;
21#[doc = "Field `CHIP_CPU_FREQ_LOW` writer - "]
22pub type CHIP_CPU_FREQ_LOW_W<'a, REG> = crate::BitWriter<'a, REG>;
23#[doc = "Field `CHIP_CPU_FREQ_RATED` reader - "]
24pub type CHIP_CPU_FREQ_RATED_R = crate::BitReader;
25#[doc = "Field `CHIP_CPU_FREQ_RATED` writer - "]
26pub type CHIP_CPU_FREQ_RATED_W<'a, REG> = crate::BitWriter<'a, REG>;
27#[doc = "Field `BLK3_PART_RESERVE` reader - "]
28pub type BLK3_PART_RESERVE_R = crate::BitReader;
29#[doc = "Field `BLK3_PART_RESERVE` writer - "]
30pub type BLK3_PART_RESERVE_W<'a, REG> = crate::BitWriter<'a, REG>;
31#[doc = "Field `CHIP_VER_REV1` reader - "]
32pub type CHIP_VER_REV1_R = crate::BitReader;
33#[doc = "Field `CHIP_VER_REV1` writer - "]
34pub type CHIP_VER_REV1_W<'a, REG> = crate::BitWriter<'a, REG>;
35#[doc = "Field `RESERVE_0_112` reader - "]
36pub type RESERVE_0_112_R = crate::FieldReader<u16>;
37#[doc = "Field `RESERVE_0_112` writer - "]
38pub type RESERVE_0_112_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
39impl R {
40    #[doc = "Bit 0"]
41    #[inline(always)]
42    pub fn disable_app_cpu(&self) -> DISABLE_APP_CPU_R {
43        DISABLE_APP_CPU_R::new((self.bits & 1) != 0)
44    }
45    #[doc = "Bit 1"]
46    #[inline(always)]
47    pub fn disable_bt(&self) -> DISABLE_BT_R {
48        DISABLE_BT_R::new(((self.bits >> 1) & 1) != 0)
49    }
50    #[doc = "Bit 2"]
51    #[inline(always)]
52    pub fn chip_package_4bit(&self) -> CHIP_PACKAGE_4BIT_R {
53        CHIP_PACKAGE_4BIT_R::new(((self.bits >> 2) & 1) != 0)
54    }
55    #[doc = "Bit 3"]
56    #[inline(always)]
57    pub fn dis_cache(&self) -> DIS_CACHE_R {
58        DIS_CACHE_R::new(((self.bits >> 3) & 1) != 0)
59    }
60    #[doc = "Bits 4:8"]
61    #[inline(always)]
62    pub fn spi_pad_config_hd(&self) -> SPI_PAD_CONFIG_HD_R {
63        SPI_PAD_CONFIG_HD_R::new(((self.bits >> 4) & 0x1f) as u8)
64    }
65    #[doc = "Bits 9:11"]
66    #[inline(always)]
67    pub fn chip_package(&self) -> CHIP_PACKAGE_R {
68        CHIP_PACKAGE_R::new(((self.bits >> 9) & 7) as u8)
69    }
70    #[doc = "Bit 12"]
71    #[inline(always)]
72    pub fn chip_cpu_freq_low(&self) -> CHIP_CPU_FREQ_LOW_R {
73        CHIP_CPU_FREQ_LOW_R::new(((self.bits >> 12) & 1) != 0)
74    }
75    #[doc = "Bit 13"]
76    #[inline(always)]
77    pub fn chip_cpu_freq_rated(&self) -> CHIP_CPU_FREQ_RATED_R {
78        CHIP_CPU_FREQ_RATED_R::new(((self.bits >> 13) & 1) != 0)
79    }
80    #[doc = "Bit 14"]
81    #[inline(always)]
82    pub fn blk3_part_reserve(&self) -> BLK3_PART_RESERVE_R {
83        BLK3_PART_RESERVE_R::new(((self.bits >> 14) & 1) != 0)
84    }
85    #[doc = "Bit 15"]
86    #[inline(always)]
87    pub fn chip_ver_rev1(&self) -> CHIP_VER_REV1_R {
88        CHIP_VER_REV1_R::new(((self.bits >> 15) & 1) != 0)
89    }
90    #[doc = "Bits 16:31"]
91    #[inline(always)]
92    pub fn reserve_0_112(&self) -> RESERVE_0_112_R {
93        RESERVE_0_112_R::new(((self.bits >> 16) & 0xffff) as u16)
94    }
95}
96#[cfg(feature = "impl-register-debug")]
97impl core::fmt::Debug for R {
98    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
99        f.debug_struct("BLK0_WDATA3")
100            .field("disable_app_cpu", &self.disable_app_cpu())
101            .field("disable_bt", &self.disable_bt())
102            .field("chip_package_4bit", &self.chip_package_4bit())
103            .field("dis_cache", &self.dis_cache())
104            .field("spi_pad_config_hd", &self.spi_pad_config_hd())
105            .field("chip_package", &self.chip_package())
106            .field("chip_cpu_freq_low", &self.chip_cpu_freq_low())
107            .field("chip_cpu_freq_rated", &self.chip_cpu_freq_rated())
108            .field("blk3_part_reserve", &self.blk3_part_reserve())
109            .field("chip_ver_rev1", &self.chip_ver_rev1())
110            .field("reserve_0_112", &self.reserve_0_112())
111            .finish()
112    }
113}
114impl W {
115    #[doc = "Bits 9:11"]
116    #[inline(always)]
117    pub fn chip_package(&mut self) -> CHIP_PACKAGE_W<BLK0_WDATA3_SPEC> {
118        CHIP_PACKAGE_W::new(self, 9)
119    }
120    #[doc = "Bit 12"]
121    #[inline(always)]
122    pub fn chip_cpu_freq_low(&mut self) -> CHIP_CPU_FREQ_LOW_W<BLK0_WDATA3_SPEC> {
123        CHIP_CPU_FREQ_LOW_W::new(self, 12)
124    }
125    #[doc = "Bit 13"]
126    #[inline(always)]
127    pub fn chip_cpu_freq_rated(&mut self) -> CHIP_CPU_FREQ_RATED_W<BLK0_WDATA3_SPEC> {
128        CHIP_CPU_FREQ_RATED_W::new(self, 13)
129    }
130    #[doc = "Bit 14"]
131    #[inline(always)]
132    pub fn blk3_part_reserve(&mut self) -> BLK3_PART_RESERVE_W<BLK0_WDATA3_SPEC> {
133        BLK3_PART_RESERVE_W::new(self, 14)
134    }
135    #[doc = "Bit 15"]
136    #[inline(always)]
137    pub fn chip_ver_rev1(&mut self) -> CHIP_VER_REV1_W<BLK0_WDATA3_SPEC> {
138        CHIP_VER_REV1_W::new(self, 15)
139    }
140    #[doc = "Bits 16:31"]
141    #[inline(always)]
142    pub fn reserve_0_112(&mut self) -> RESERVE_0_112_W<BLK0_WDATA3_SPEC> {
143        RESERVE_0_112_W::new(self, 16)
144    }
145}
146#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`blk0_wdata3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`blk0_wdata3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
147pub struct BLK0_WDATA3_SPEC;
148impl crate::RegisterSpec for BLK0_WDATA3_SPEC {
149    type Ux = u32;
150}
151#[doc = "`read()` method returns [`blk0_wdata3::R`](R) reader structure"]
152impl crate::Readable for BLK0_WDATA3_SPEC {}
153#[doc = "`write(|w| ..)` method takes [`blk0_wdata3::W`](W) writer structure"]
154impl crate::Writable for BLK0_WDATA3_SPEC {
155    type Safety = crate::Unsafe;
156    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
157    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
158}
159#[doc = "`reset()` method sets BLK0_WDATA3 to value 0"]
160impl crate::Resettable for BLK0_WDATA3_SPEC {
161    const RESET_VALUE: u32 = 0;
162}
esp32/efuse/blk0_wdata3.rs

esp32/efuse/
blk0_wdata3.rs
