Module ctrl1

Structs

CTRL1_SPEC

You can read this register and get ctrl1::R. You can reset, write, write_with_zero this register using ctrl1::W. You can also modify this register. See API.

Type Aliases

CS_HOLD_DELAY_R

Field CS_HOLD_DELAY reader - SPI cs signal is delayed by spi clock cycles

CS_HOLD_DELAY_RES_R

Field CS_HOLD_DELAY_RES reader - Delay cycles of resume Flash when resume Flash is enable by spi clock.

CS_HOLD_DELAY_RES_W

Field CS_HOLD_DELAY_RES writer - Delay cycles of resume Flash when resume Flash is enable by spi clock.

CS_HOLD_DELAY_W

Field CS_HOLD_DELAY writer - SPI cs signal is delayed by spi clock cycles

R

Register CTRL1 reader

W

Register CTRL1 writer