esp32

Module emac_dma

Source
Expand description

Ethernet DMA configuration and control registers

Modules§

  • dmabusmode
    Bus mode configuration
  • dmain_en
  • dmamissedfr
    Missed Frame and Buffer Overflow Counter Register
  • dmaoperation_mode
    Receive and Transmit operating modes and command
  • dmarintwdtimer
    Watchdog timer count on receive
  • dmarxbaseaddr
    This field contains the base address of the first descriptor in the Receive Descriptor list. The LSB Bits[1:0] are ignored and internally taken as all-zero by the DMA. Therefore these LSB bits are read-only.
  • dmarxcurraddr_buf
    The address of the current receive descriptor list. Cleared on Reset.Pointer updated by the DMA during operation.
  • dmarxcurrdesc
    The address of the current receive descriptor list. Cleared on Reset.Pointer updated by the DMA during operation.
  • dmarxpolldemand
    When these bits are written with any value the DMA reads the current descriptor to which the Current Host Receive Descriptor Register is pointing. If that descriptor is not available (owned by the Host) the reception returns to the Suspended state and Bit[7] (RU) of Status Register is asserted. If the descriptor is available the Rx DMA returns to the active state.
  • dmastatus
    State of interrupts, errors and other events
  • dmatxbaseaddr
    This field contains the base address of the first descriptor in the Transmit Descriptor list. The LSB Bits[1:0] are ignored and are internally taken as all-zero by the DMA.Therefore these LSB bits are read-only.
  • dmatxcurraddr_buf
    The address of the current receive descriptor list. Cleared on Reset.Pointer updated by the DMA during operation.
  • dmatxcurrdesc
    The address of the current receive descriptor list. Cleared on Reset.Pointer updated by the DMA during operation.
  • dmatxpolldemand
    When these bits are written with any value the DMA reads the current descriptor to which the Register (Current Host Transmit Descriptor Register) is pointing. If that descriptor is not available (owned by the Host) the transmission returns to the suspend state and Bit[2] (TU) of Status Register is asserted. If the descriptor is available the transmission resumes.

Structs§

Type Aliases§

  • DMABUSMODE
    DMABUSMODE (rw) register accessor: Bus mode configuration
  • DMAIN_EN
    DMAIN_EN (rw) register accessor:
  • DMAMISSEDFR
    DMAMISSEDFR (rw) register accessor: Missed Frame and Buffer Overflow Counter Register
  • DMAOPERATION_MODE
    DMAOPERATION_MODE (rw) register accessor: Receive and Transmit operating modes and command
  • DMARINTWDTIMER
    DMARINTWDTIMER (rw) register accessor: Watchdog timer count on receive
  • DMARXBASEADDR
    DMARXBASEADDR (rw) register accessor: This field contains the base address of the first descriptor in the Receive Descriptor list. The LSB Bits[1:0] are ignored and internally taken as all-zero by the DMA. Therefore these LSB bits are read-only.
  • DMARXCURRADDR_BUF
    DMARXCURRADDR_BUF (r) register accessor: The address of the current receive descriptor list. Cleared on Reset.Pointer updated by the DMA during operation.
  • DMARXCURRDESC
    DMARXCURRDESC (r) register accessor: The address of the current receive descriptor list. Cleared on Reset.Pointer updated by the DMA during operation.
  • DMARXPOLLDEMAND
    DMARXPOLLDEMAND (r) register accessor: When these bits are written with any value the DMA reads the current descriptor to which the Current Host Receive Descriptor Register is pointing. If that descriptor is not available (owned by the Host) the reception returns to the Suspended state and Bit[7] (RU) of Status Register is asserted. If the descriptor is available the Rx DMA returns to the active state.
  • DMASTATUS
    DMASTATUS (rw) register accessor: State of interrupts, errors and other events
  • DMATXBASEADDR
    DMATXBASEADDR (rw) register accessor: This field contains the base address of the first descriptor in the Transmit Descriptor list. The LSB Bits[1:0] are ignored and are internally taken as all-zero by the DMA.Therefore these LSB bits are read-only.
  • DMATXCURRADDR_BUF
    DMATXCURRADDR_BUF (r) register accessor: The address of the current receive descriptor list. Cleared on Reset.Pointer updated by the DMA during operation.
  • DMATXCURRDESC
    DMATXCURRDESC (r) register accessor: The address of the current receive descriptor list. Cleared on Reset.Pointer updated by the DMA during operation.
  • DMATXPOLLDEMAND
    DMATXPOLLDEMAND (r) register accessor: When these bits are written with any value the DMA reads the current descriptor to which the Register (Current Host Transmit Descriptor Register) is pointing. If that descriptor is not available (owned by the Host) the transmission returns to the suspend state and Bit[2] (TU) of Status Register is asserted. If the descriptor is available the transmission resumes.