1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
#[doc = "Register `CTRL2` reader"]
pub struct R(crate::R<CTRL2_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CTRL2_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CTRL2_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CTRL2_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CTRL2` writer"]
pub struct W(crate::W<CTRL2_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CTRL2_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CTRL2_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CTRL2_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `SETUP_TIME` reader - (cycles-1) of ¡°prepare¡± phase by spi clock, this bits combined with spi_cs_setup bit."]
pub type SETUP_TIME_R = crate::FieldReader<u8, u8>;
#[doc = "Field `SETUP_TIME` writer - (cycles-1) of ¡°prepare¡± phase by spi clock, this bits combined with spi_cs_setup bit."]
pub type SETUP_TIME_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CTRL2_SPEC, u8, u8, 4, O>;
#[doc = "Field `HOLD_TIME` reader - delay cycles of cs pin by spi clock, this bits combined with spi_cs_hold bit."]
pub type HOLD_TIME_R = crate::FieldReader<u8, u8>;
#[doc = "Field `HOLD_TIME` writer - delay cycles of cs pin by spi clock, this bits combined with spi_cs_hold bit."]
pub type HOLD_TIME_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CTRL2_SPEC, u8, u8, 4, O>;
#[doc = "Field `CK_OUT_LOW_MODE` reader - modify spi clock duty ratio when the value is lager than 8, the bits are combined with spi_clkcnt_N bits and spi_clkcnt_L bits."]
pub type CK_OUT_LOW_MODE_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CK_OUT_LOW_MODE` writer - modify spi clock duty ratio when the value is lager than 8, the bits are combined with spi_clkcnt_N bits and spi_clkcnt_L bits."]
pub type CK_OUT_LOW_MODE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CTRL2_SPEC, u8, u8, 4, O>;
#[doc = "Field `CK_OUT_HIGH_MODE` reader - modify spi clock duty ratio when the value is lager than 8, the bits are combined with spi_clkcnt_N bits and spi_clkcnt_H bits."]
pub type CK_OUT_HIGH_MODE_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CK_OUT_HIGH_MODE` writer - modify spi clock duty ratio when the value is lager than 8, the bits are combined with spi_clkcnt_N bits and spi_clkcnt_H bits."]
pub type CK_OUT_HIGH_MODE_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CTRL2_SPEC, u8, u8, 4, O>;
#[doc = "Field `MISO_DELAY_MODE` reader - MISO signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle"]
pub type MISO_DELAY_MODE_R = crate::FieldReader<u8, u8>;
#[doc = "Field `MISO_DELAY_MODE` writer - MISO signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle"]
pub type MISO_DELAY_MODE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CTRL2_SPEC, u8, u8, 2, O>;
#[doc = "Field `MISO_DELAY_NUM` reader - MISO signals are delayed by system clock cycles"]
pub type MISO_DELAY_NUM_R = crate::FieldReader<u8, u8>;
#[doc = "Field `MISO_DELAY_NUM` writer - MISO signals are delayed by system clock cycles"]
pub type MISO_DELAY_NUM_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CTRL2_SPEC, u8, u8, 3, O>;
#[doc = "Field `MOSI_DELAY_MODE` reader - MOSI signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle"]
pub type MOSI_DELAY_MODE_R = crate::FieldReader<u8, u8>;
#[doc = "Field `MOSI_DELAY_MODE` writer - MOSI signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle"]
pub type MOSI_DELAY_MODE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CTRL2_SPEC, u8, u8, 2, O>;
#[doc = "Field `MOSI_DELAY_NUM` reader - MOSI signals are delayed by system clock cycles"]
pub type MOSI_DELAY_NUM_R = crate::FieldReader<u8, u8>;
#[doc = "Field `MOSI_DELAY_NUM` writer - MOSI signals are delayed by system clock cycles"]
pub type MOSI_DELAY_NUM_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CTRL2_SPEC, u8, u8, 3, O>;
#[doc = "Field `CS_DELAY_MODE` reader - spi_cs signal is delayed by spi_clk . 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle"]
pub type CS_DELAY_MODE_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CS_DELAY_MODE` writer - spi_cs signal is delayed by spi_clk . 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle"]
pub type CS_DELAY_MODE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CTRL2_SPEC, u8, u8, 2, O>;
#[doc = "Field `CS_DELAY_NUM` reader - spi_cs signal is delayed by system clock cycles"]
pub type CS_DELAY_NUM_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CS_DELAY_NUM` writer - spi_cs signal is delayed by system clock cycles"]
pub type CS_DELAY_NUM_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CTRL2_SPEC, u8, u8, 4, O>;
impl R {
#[doc = "Bits 0:3 - (cycles-1) of ¡°prepare¡± phase by spi clock, this bits combined with spi_cs_setup bit."]
#[inline(always)]
pub fn setup_time(&self) -> SETUP_TIME_R {
SETUP_TIME_R::new((self.bits & 0x0f) as u8)
}
#[doc = "Bits 4:7 - delay cycles of cs pin by spi clock, this bits combined with spi_cs_hold bit."]
#[inline(always)]
pub fn hold_time(&self) -> HOLD_TIME_R {
HOLD_TIME_R::new(((self.bits >> 4) & 0x0f) as u8)
}
#[doc = "Bits 8:11 - modify spi clock duty ratio when the value is lager than 8, the bits are combined with spi_clkcnt_N bits and spi_clkcnt_L bits."]
#[inline(always)]
pub fn ck_out_low_mode(&self) -> CK_OUT_LOW_MODE_R {
CK_OUT_LOW_MODE_R::new(((self.bits >> 8) & 0x0f) as u8)
}
#[doc = "Bits 12:15 - modify spi clock duty ratio when the value is lager than 8, the bits are combined with spi_clkcnt_N bits and spi_clkcnt_H bits."]
#[inline(always)]
pub fn ck_out_high_mode(&self) -> CK_OUT_HIGH_MODE_R {
CK_OUT_HIGH_MODE_R::new(((self.bits >> 12) & 0x0f) as u8)
}
#[doc = "Bits 16:17 - MISO signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle"]
#[inline(always)]
pub fn miso_delay_mode(&self) -> MISO_DELAY_MODE_R {
MISO_DELAY_MODE_R::new(((self.bits >> 16) & 3) as u8)
}
#[doc = "Bits 18:20 - MISO signals are delayed by system clock cycles"]
#[inline(always)]
pub fn miso_delay_num(&self) -> MISO_DELAY_NUM_R {
MISO_DELAY_NUM_R::new(((self.bits >> 18) & 7) as u8)
}
#[doc = "Bits 21:22 - MOSI signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle"]
#[inline(always)]
pub fn mosi_delay_mode(&self) -> MOSI_DELAY_MODE_R {
MOSI_DELAY_MODE_R::new(((self.bits >> 21) & 3) as u8)
}
#[doc = "Bits 23:25 - MOSI signals are delayed by system clock cycles"]
#[inline(always)]
pub fn mosi_delay_num(&self) -> MOSI_DELAY_NUM_R {
MOSI_DELAY_NUM_R::new(((self.bits >> 23) & 7) as u8)
}
#[doc = "Bits 26:27 - spi_cs signal is delayed by spi_clk . 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle"]
#[inline(always)]
pub fn cs_delay_mode(&self) -> CS_DELAY_MODE_R {
CS_DELAY_MODE_R::new(((self.bits >> 26) & 3) as u8)
}
#[doc = "Bits 28:31 - spi_cs signal is delayed by system clock cycles"]
#[inline(always)]
pub fn cs_delay_num(&self) -> CS_DELAY_NUM_R {
CS_DELAY_NUM_R::new(((self.bits >> 28) & 0x0f) as u8)
}
}
impl W {
#[doc = "Bits 0:3 - (cycles-1) of ¡°prepare¡± phase by spi clock, this bits combined with spi_cs_setup bit."]
#[inline(always)]
#[must_use]
pub fn setup_time(&mut self) -> SETUP_TIME_W<0> {
SETUP_TIME_W::new(self)
}
#[doc = "Bits 4:7 - delay cycles of cs pin by spi clock, this bits combined with spi_cs_hold bit."]
#[inline(always)]
#[must_use]
pub fn hold_time(&mut self) -> HOLD_TIME_W<4> {
HOLD_TIME_W::new(self)
}
#[doc = "Bits 8:11 - modify spi clock duty ratio when the value is lager than 8, the bits are combined with spi_clkcnt_N bits and spi_clkcnt_L bits."]
#[inline(always)]
#[must_use]
pub fn ck_out_low_mode(&mut self) -> CK_OUT_LOW_MODE_W<8> {
CK_OUT_LOW_MODE_W::new(self)
}
#[doc = "Bits 12:15 - modify spi clock duty ratio when the value is lager than 8, the bits are combined with spi_clkcnt_N bits and spi_clkcnt_H bits."]
#[inline(always)]
#[must_use]
pub fn ck_out_high_mode(&mut self) -> CK_OUT_HIGH_MODE_W<12> {
CK_OUT_HIGH_MODE_W::new(self)
}
#[doc = "Bits 16:17 - MISO signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle"]
#[inline(always)]
#[must_use]
pub fn miso_delay_mode(&mut self) -> MISO_DELAY_MODE_W<16> {
MISO_DELAY_MODE_W::new(self)
}
#[doc = "Bits 18:20 - MISO signals are delayed by system clock cycles"]
#[inline(always)]
#[must_use]
pub fn miso_delay_num(&mut self) -> MISO_DELAY_NUM_W<18> {
MISO_DELAY_NUM_W::new(self)
}
#[doc = "Bits 21:22 - MOSI signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle"]
#[inline(always)]
#[must_use]
pub fn mosi_delay_mode(&mut self) -> MOSI_DELAY_MODE_W<21> {
MOSI_DELAY_MODE_W::new(self)
}
#[doc = "Bits 23:25 - MOSI signals are delayed by system clock cycles"]
#[inline(always)]
#[must_use]
pub fn mosi_delay_num(&mut self) -> MOSI_DELAY_NUM_W<23> {
MOSI_DELAY_NUM_W::new(self)
}
#[doc = "Bits 26:27 - spi_cs signal is delayed by spi_clk . 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle"]
#[inline(always)]
#[must_use]
pub fn cs_delay_mode(&mut self) -> CS_DELAY_MODE_W<26> {
CS_DELAY_MODE_W::new(self)
}
#[doc = "Bits 28:31 - spi_cs signal is delayed by system clock cycles"]
#[inline(always)]
#[must_use]
pub fn cs_delay_num(&mut self) -> CS_DELAY_NUM_W<28> {
CS_DELAY_NUM_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl2](index.html) module"]
pub struct CTRL2_SPEC;
impl crate::RegisterSpec for CTRL2_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [ctrl2::R](R) reader structure"]
impl crate::Readable for CTRL2_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [ctrl2::W](W) writer structure"]
impl crate::Writable for CTRL2_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CTRL2 to value 0x11"]
impl crate::Resettable for CTRL2_SPEC {
const RESET_VALUE: Self::Ux = 0x11;
}